From patchwork Wed Aug 29 19:36:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10580851 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5558F17DE for ; Wed, 29 Aug 2018 19:37:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 461A22BA00 for ; Wed, 29 Aug 2018 19:37:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3A12A2BB13; Wed, 29 Aug 2018 19:37:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DAC4B2BA00 for ; Wed, 29 Aug 2018 19:37:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 51AA36E5F8; Wed, 29 Aug 2018 19:37:09 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 956276E5F2 for ; Wed, 29 Aug 2018 19:36:56 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Aug 2018 12:36:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,304,1531810800"; d="scan'208";a="86016437" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga001.jf.intel.com with ESMTP; 29 Aug 2018 12:36:40 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [172.28.181.6]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id w7TJaZPP026766 for ; Wed, 29 Aug 2018 20:36:39 +0100 From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Wed, 29 Aug 2018 19:36:29 +0000 Message-Id: <20180829193634.37060-17-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20180829193634.37060-1-michal.wajdeczko@intel.com> References: <20180829193634.37060-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [CI 16/21] drm/i915/guc: New engine-reset-complete message X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP GuC sends ENGINE_RESET_COMPLETE message as an follow-up answer to earlier ENGINE_RESET request from the host. Once this message is received, clear engine reset flag to unblock our reset process. Credits-to: Michel Thierry Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Michel Thierry Cc: Vinay Belgaumkar Cc: Michal Winiarski Cc: Tomasz Lis --- drivers/gpu/drm/i915/intel_guc.c | 29 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_guc_fwif.h | 3 ++- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index da61115..9a177ff 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -27,6 +27,9 @@ #include "intel_guc_submission.h" #include "i915_drv.h" +static void guc_handle_engine_reset_completed(struct intel_guc *guc, + const u32 engine_class); + static void gen8_guc_raise_irq(struct intel_guc *guc) { struct drm_i915_private *dev_priv = guc_to_i915(guc); @@ -528,6 +531,12 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc *guc, INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)) intel_guc_log_handle_flush_event(&guc->log); + if (msg & INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE) { + if (len != 3) + return -EPROTO; + guc_handle_engine_reset_completed(guc, payload[1]); + } + return 0; } @@ -588,6 +597,7 @@ int intel_guc_suspend(struct intel_guc *guc) { GEM_BUG_ON(guc_class >= GUC_MAX_ENGINE_CLASSES); bitmap32_set_bit(&guc->engine_class_under_reset, guc_class); + intel_guc_enable_msg(guc, INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE); } static inline void @@ -595,6 +605,7 @@ int intel_guc_suspend(struct intel_guc *guc) { GEM_BUG_ON(guc_class >= GUC_MAX_ENGINE_CLASSES); bitmap32_clear_bit(&guc->engine_class_under_reset, guc_class); + intel_guc_disable_msg(guc, INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE); } static inline bool @@ -659,6 +670,24 @@ int intel_guc_reset_engine(struct intel_guc *guc, return ret; } +/* + * GuC notifies host that reset engine has completed. + * This message should only be received after a request-reset h2g, + * so check that and clear the engine_class_under_reset flag. + */ +static void guc_handle_engine_reset_completed(struct intel_guc *guc, + const u32 engine_class) +{ + if (engine_class >= GUC_MAX_ENGINE_CLASSES || + !guc_is_class_under_reset(guc, engine_class)) { + DRM_WARN("Unexpected reset-complete for engine class: %d", + engine_class); + return; + } + + guc_clear_class_under_reset(guc, engine_class); +} + /** * intel_guc_resume() - notify GuC resuming from suspend state * @guc: the guc diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 156db08..1958581 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -757,7 +757,8 @@ enum intel_guc_response_status { /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ enum intel_guc_recv_message { INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), - INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3) + INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3), + INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE = BIT(25), }; #endif