From patchwork Wed Aug 29 19:36:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10580833 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1838217DE for ; Wed, 29 Aug 2018 19:36:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0AC9028538 for ; Wed, 29 Aug 2018 19:36:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F341B2BA52; Wed, 29 Aug 2018 19:36:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8198728538 for ; Wed, 29 Aug 2018 19:36:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4F02F6E5E6; Wed, 29 Aug 2018 19:36:41 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9B4F56E5DB for ; Wed, 29 Aug 2018 19:36:38 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Aug 2018 12:36:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,304,1531810800"; d="scan'208";a="66134947" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga007.fm.intel.com with ESMTP; 29 Aug 2018 12:36:37 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [172.28.181.6]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id w7TJaZPF026766 for ; Wed, 29 Aug 2018 20:36:36 +0100 From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Wed, 29 Aug 2018 19:36:19 +0000 Message-Id: <20180829193634.37060-7-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20180829193634.37060-1-michal.wajdeczko@intel.com> References: <20180829193634.37060-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [CI 06/21] drm/i915/guc: Use guc_class instead of engine_class in fw interface X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Until now the GuC and HW engine class has been the same, which allowed us to use them interchangeable. But it is better to start doing the right thing and use the GuC definitions for the firmware interface. We also keep the same class id in the ctx descriptor to be able to have the same values in the driver and firmware logs. Signed-off-by: Michel Thierry Signed-off-by: Rodrigo Vivi Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Michel Thierry Cc: Lucas De Marchi Cc: Tomasz Lis --- drivers/gpu/drm/i915/intel_engine_cs.c | 13 +++++++++++++ drivers/gpu/drm/i915/intel_guc_fwif.h | 7 +++++++ drivers/gpu/drm/i915/intel_lrc.c | 10 +++++++++- drivers/gpu/drm/i915/intel_ringbuffer.h | 2 ++ 4 files changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 1a34e8f..bc81354 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -85,6 +85,7 @@ struct engine_info { unsigned int hw_id; unsigned int uabi_id; u8 class; + u8 guc_class; u8 instance; /* mmio bases table *must* be sorted in reverse gen order */ struct engine_mmio_base { @@ -98,6 +99,7 @@ struct engine_info { .hw_id = RCS_HW, .uabi_id = I915_EXEC_RENDER, .class = RENDER_CLASS, + .guc_class = GUC_RENDER_CLASS, .instance = 0, .mmio_bases = { { .gen = 1, .base = RENDER_RING_BASE } @@ -107,6 +109,7 @@ struct engine_info { .hw_id = BCS_HW, .uabi_id = I915_EXEC_BLT, .class = COPY_ENGINE_CLASS, + .guc_class = GUC_BLITTER_CLASS, .instance = 0, .mmio_bases = { { .gen = 6, .base = BLT_RING_BASE } @@ -116,6 +119,7 @@ struct engine_info { .hw_id = VCS_HW, .uabi_id = I915_EXEC_BSD, .class = VIDEO_DECODE_CLASS, + .guc_class = GUC_VIDEO_CLASS, .instance = 0, .mmio_bases = { { .gen = 11, .base = GEN11_BSD_RING_BASE }, @@ -127,6 +131,7 @@ struct engine_info { .hw_id = VCS2_HW, .uabi_id = I915_EXEC_BSD, .class = VIDEO_DECODE_CLASS, + .guc_class = GUC_VIDEO_CLASS, .instance = 1, .mmio_bases = { { .gen = 11, .base = GEN11_BSD2_RING_BASE }, @@ -137,6 +142,7 @@ struct engine_info { .hw_id = VCS3_HW, .uabi_id = I915_EXEC_BSD, .class = VIDEO_DECODE_CLASS, + .guc_class = GUC_VIDEO_CLASS, .instance = 2, .mmio_bases = { { .gen = 11, .base = GEN11_BSD3_RING_BASE } @@ -146,6 +152,7 @@ struct engine_info { .hw_id = VCS4_HW, .uabi_id = I915_EXEC_BSD, .class = VIDEO_DECODE_CLASS, + .guc_class = GUC_VIDEO_CLASS, .instance = 3, .mmio_bases = { { .gen = 11, .base = GEN11_BSD4_RING_BASE } @@ -155,6 +162,7 @@ struct engine_info { .hw_id = VECS_HW, .uabi_id = I915_EXEC_VEBOX, .class = VIDEO_ENHANCEMENT_CLASS, + .guc_class = GUC_VIDEOENHANCE_CLASS, .instance = 0, .mmio_bases = { { .gen = 11, .base = GEN11_VEBOX_RING_BASE }, @@ -165,6 +173,7 @@ struct engine_info { .hw_id = VECS2_HW, .uabi_id = I915_EXEC_VEBOX, .class = VIDEO_ENHANCEMENT_CLASS, + .guc_class = GUC_VIDEOENHANCE_CLASS, .instance = 1, .mmio_bases = { { .gen = 11, .base = GEN11_VEBOX2_RING_BASE } @@ -276,6 +285,9 @@ static void __sprint_engine_name(char *name, const struct engine_info *info) if (GEM_WARN_ON(info->class > MAX_ENGINE_CLASS)) return -EINVAL; + if (GEM_WARN_ON(info->guc_class >= GUC_MAX_ENGINE_CLASSES)) + return -EINVAL; + if (GEM_WARN_ON(info->instance > MAX_ENGINE_INSTANCE)) return -EINVAL; @@ -291,6 +303,7 @@ static void __sprint_engine_name(char *name, const struct engine_info *info) engine->i915 = dev_priv; __sprint_engine_name(engine->name, info); engine->hw_id = engine->guc_id = info->hw_id; + engine->guc_class = info->guc_class; engine->mmio_base = __engine_mmio_base(dev_priv, info->mmio_bases); engine->class = info->class; engine->instance = info->instance; diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 963da91..5b7a05b 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -39,6 +39,13 @@ #define GUC_VIDEO_ENGINE2 4 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1) +#define GUC_RENDER_CLASS 0 +#define GUC_VIDEO_CLASS 1 +#define GUC_VIDEOENHANCE_CLASS 2 +#define GUC_BLITTER_CLASS 3 +#define GUC_RESERVED_CLASS 4 +#define GUC_MAX_ENGINE_CLASSES (GUC_RESERVED_CLASS + 1) + /* Work queue item header definitions */ #define WQ_STATUS_ACTIVE 1 #define WQ_STATUS_SUSPENDED 2 diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index f8ceb9c..f4b9972 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -249,7 +249,15 @@ static inline bool need_preempt(const struct intel_engine_cs *engine, /* TODO: decide what to do with SW counter (bits 55-60) */ - desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT; + /* + * Although GuC will never see this upper part as it fills + * its own descriptor, using the guc_class here will help keep + * the i915 and firmware logs in sync. + */ + if (HAS_GUC_SCHED(ctx->i915)) + desc |= (u64)engine->guc_class << GEN11_ENGINE_CLASS_SHIFT; + else + desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT; /* bits 61-63 */ } else { GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH)); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 3f6920d..f47009f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -350,7 +350,9 @@ struct intel_engine_cs { enum intel_engine_id id; unsigned int hw_id; + unsigned int guc_id; + u8 guc_class; u8 uabi_id; u8 uabi_class;