From patchwork Wed Sep 5 14:22:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10588971 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D4B1E112B for ; Wed, 5 Sep 2018 14:22:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BF7272A2FC for ; Wed, 5 Sep 2018 14:22:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B341B2A2DA; Wed, 5 Sep 2018 14:22:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6BAD42A2DA for ; Wed, 5 Sep 2018 14:22:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 422FD6E4C4; Wed, 5 Sep 2018 14:22:35 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) by gabe.freedesktop.org (Postfix) with ESMTPS id 641CB6E4BD for ; Wed, 5 Sep 2018 14:22:33 +0000 (UTC) Received: by mail-wm0-x241.google.com with SMTP id n11-v6so7927361wmc.2 for ; Wed, 05 Sep 2018 07:22:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lNOSq62IzwEbWURvB608LNDbusaDOstHXemnYnCltYY=; b=gPr4BzyD32aESMdjbArzgZsPVR8D8+qJyt3EZkCzZ6gBwwgrpjDEmdGKO6bEbT+ewL jwZyPfkXqgMyFxAVcNuIkTlk2hq6vQNxlvEiVQD1ijNM3PLK/W+C/Jay8IDCdHkjKsoB 8uA4wjHySEDy5DlmVcoaPFeBGF1xIiiVm01JTrE0khDrtv5yhK0/1F2eDGeEXQco6lhh Vg1U/kjRHYU9Ghadt/WvzIPwSQ+RRBtljm1HBx/gaQYB9B2MfpsJgyx5RxaCxAvURKaV WZ2IGHcR0thhehQzNNA3gf3g8oeEMc0G+ObryYykLa7TVtO6MxMjUjRY+Sj6m3IJqIq9 w1BQ== X-Gm-Message-State: APzg51DTiHPJM43qm/rE1IcpVgxIE8k0iRs93XDZHrRYX1XOU8w9Fjh4 43ccDl2vDJTpSlyPV4NbmLmFS2EJIbo= X-Google-Smtp-Source: ANB0VdZEj9HucXJ/kWditpx4bhIz5swI6vy9pUAHrdY++F/NeG1vTk78B+EmTGX1kI6Uz8E4/+QFRw== X-Received: by 2002:a1c:7015:: with SMTP id l21-v6mr372349wmc.81.1536157351900; Wed, 05 Sep 2018 07:22:31 -0700 (PDT) Received: from localhost.localdomain ([95.144.165.37]) by smtp.gmail.com with ESMTPSA id x125-v6sm2851438wmg.27.2018.09.05.07.22.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Sep 2018 07:22:31 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Wed, 5 Sep 2018 15:22:16 +0100 Message-Id: <20180905142222.3251-2-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180905142222.3251-1-tvrtko.ursulin@linux.intel.com> References: <20180905142222.3251-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH 1/7] drm/i915/execlists: Move RPCS setup to context pin X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Configuring RPCS in context image just before pin is sufficient and will come extra handy in one of the following patches. v2: * Split image setup a bit differently. (Chris Wilson) Signed-off-by: Tvrtko Ursulin Suggested-by: Chris Wilson Cc: Chris Wilson Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/intel_lrc.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 9b1f0e5211a0..358fad63564c 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1305,6 +1305,8 @@ static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma) return i915_vma_pin(vma, 0, 0, flags); } +static u32 make_rpcs(struct drm_i915_private *dev_priv); + static struct intel_context * __execlists_context_pin(struct intel_engine_cs *engine, struct i915_gem_context *ctx, @@ -1344,6 +1346,12 @@ __execlists_context_pin(struct intel_engine_cs *engine, GEM_BUG_ON(!intel_ring_offset_valid(ce->ring, ce->ring->head)); ce->lrc_reg_state[CTX_RING_HEAD+1] = ce->ring->head; + /* RPCS */ + if (engine->class == RENDER_CLASS) { + ce->lrc_reg_state[CTX_R_PWR_CLK_STATE + 1] = + make_rpcs(engine->i915); + } + ce->state->obj->pin_global++; i915_gem_context_get(ctx); return ce; @@ -2706,8 +2714,7 @@ static void execlists_init_reg_state(u32 *regs, if (rcs) { regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); - CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, - make_rpcs(dev_priv)); + CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0); i915_oa_init_reg_state(engine, ctx, regs); }