From patchwork Wed Sep 5 14:22:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10588973 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E2868112B for ; Wed, 5 Sep 2018 14:22:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C8D012A2DA for ; Wed, 5 Sep 2018 14:22:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BB57B2A306; Wed, 5 Sep 2018 14:22:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 776222A2DA for ; Wed, 5 Sep 2018 14:22:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C66346E4C7; Wed, 5 Sep 2018 14:22:35 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by gabe.freedesktop.org (Postfix) with ESMTPS id 682F66E4C4 for ; Wed, 5 Sep 2018 14:22:34 +0000 (UTC) Received: by mail-wr1-x441.google.com with SMTP id m27-v6so7912347wrf.3 for ; Wed, 05 Sep 2018 07:22:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Oq0OnZ6b+w9UIW71Fin4f20WD8FI3vcqoM+hgRUxRLM=; b=CsTngInDEwRQkita3Vd35SX4IPXWBw8a+Q8LG4THroExtssAkRN8pArc5WXkoav/3M zmH/82CK6EPeda7cRtGH1BGMwaaAB/VuIVwn/KLtUpzf+2tJloE+z1wA+V7SPXGGP3cj I429l1rjIGrBW5ezVpKS0y6wpdNsrIa2A4OvVk0gw8SufV2GsB5GgsqDjeQToHprI6z4 15UVmVEuh+YZN/naVaR4EQjiyaqfoeHMzgKXf42xLGMk/dZTEkzSJXFNJ/AEWkuXQDqK jpJmxHMPc9cfF5XtWR+5HqNeJ/oa5mfUmWczfSNZc50IEYdRGoLdq8LUQcBNX4raGfze d+cA== X-Gm-Message-State: APzg51DAgZGXUP5xoZLqKkTFLlw3OWtaqp9liwokOkMyCmWVslnbp8iK Lu+77GrymtuoIW1GY0l38AxlX/S1+QA= X-Google-Smtp-Source: ANB0VdYwMWYtU9zM8Ht0rBBN6cdoLyGkELkc4MOQK5hBMQsfjdS6aFoTxdEkwHvng1PaZ4Efj95xNQ== X-Received: by 2002:a5d:6841:: with SMTP id o1-v6mr26483486wrw.159.1536157352953; Wed, 05 Sep 2018 07:22:32 -0700 (PDT) Received: from localhost.localdomain ([95.144.165.37]) by smtp.gmail.com with ESMTPSA id x125-v6sm2851438wmg.27.2018.09.05.07.22.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Sep 2018 07:22:32 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Wed, 5 Sep 2018 15:22:17 +0100 Message-Id: <20180905142222.3251-3-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180905142222.3251-1-tvrtko.ursulin@linux.intel.com> References: <20180905142222.3251-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH 2/7] drm/i915: Program RPCS for Broadwell X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Chris Wilson Currently we only configure the power gating for Skylake and above, but the configuration should equally apply to Broadwell and Braswell. Even though, there is not as much variation as for later generations, we want to expose control over the configuration to userspace and may want to opt out of the "always-enabled" setting. Signed-off-by: Chris Wilson Signed-off-by: Lionel Landwerlin Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_lrc.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 358fad63564c..3bdc1ac3e926 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2501,13 +2501,6 @@ make_rpcs(struct drm_i915_private *dev_priv) u8 subslices = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]); u32 rpcs = 0; - /* - * No explicit RPCS request is needed to ensure full - * slice/subslice/EU enablement prior to Gen9. - */ - if (INTEL_GEN(dev_priv) < 9) - return 0; - /* * Since the SScount bitfield in GEN8_R_PWR_CLK_STATE is only three bits * wide and Icelake has up to eight subslices, specfial programming is