[7/7] drm/i915/icl: Support co-existance between per-context SSEU and OA

Commit Message

Tvrtko Ursulin Sept. 5, 2018, 2:22 p.m. UTC

From: Tvrtko Ursulin <[e-mail]>

When OA is active we want to lock the powergating configuration, but on
Icelake users like media stack will have issues if we lock to the full
device configuration.

Instead lock to a subset of (sub)slices which are currently a known
working configuration for all users.

Signed-off-by: Tvrtko Ursulin <[e-mail]>
Cc: Lionel Landwerlin <[e-mail]>
---
 drivers/gpu/drm/i915/intel_lrc.c | 25 ++++++++++++++++++++-----
 1 file changed, 20 insertions(+), 5 deletions(-)

Patch

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3c85392a3109..19c9c46308e5 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2502,13 +2502,28 @@  u32 gen8_make_rpcs(struct drm_i915_private *dev_priv,
 
 	/*
 	 * If i915/perf is active, we want a stable powergating configuration
-	 * on the system. The most natural configuration to take in that case
-	 * is the default (i.e maximum the hardware can do).
+	 * on the system.
+	 *
+	 * We could choose full enablement, but on ICL we know there are use
+	 * cases which disable slices for functional, apart for performance
+	 * reasons. So in this case we select a known stable subset.
 	 */
-	if (unlikely(dev_priv->perf.oa.exclusive_stream))
-		ctx_sseu = intel_device_default_sseu(dev_priv);
-	else
+	if (!dev_priv->perf.oa.exclusive_stream) {
 		ctx_sseu = *req_sseu;
+	} else {
+		ctx_sseu = intel_device_default_sseu(dev_priv);
+
+		if (IS_GEN11(dev_priv)) {
+			/*
+			 * We only need subslice count so it doesn't matter
+			 * which ones we select - just turn of low bits in the
+			 * amount of half of all available subslices per slice.
+			 */
+			ctx_sseu.subslice_mask =
+				~(~0 << (hweight8(ctx_sseu.subslice_mask) / 2));
+			ctx_sseu.slice_mask = 0x1;
+		}
+	}
 
 	slices = hweight8(ctx_sseu.slice_mask);
 	subslices = hweight8(ctx_sseu.subslice_mask);