From patchwork Wed Sep 5 14:22:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10588983 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0DF165A4 for ; Wed, 5 Sep 2018 14:22:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EB0602A2DA for ; Wed, 5 Sep 2018 14:22:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DFDF22A2FC; Wed, 5 Sep 2018 14:22:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9A4A92A306 for ; Wed, 5 Sep 2018 14:22:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1EBE66E4D0; Wed, 5 Sep 2018 14:22:42 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by gabe.freedesktop.org (Postfix) with ESMTPS id 77F886E4D4 for ; Wed, 5 Sep 2018 14:22:40 +0000 (UTC) Received: by mail-wr1-x444.google.com with SMTP id g33-v6so7913669wrd.1 for ; Wed, 05 Sep 2018 07:22:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cQ43TgWJR2o87BI18sXJ8UmJqeDOxTLmpxHwgoUNmUM=; b=eFFc/oj4lUZ0Wdx2hcr1h5ukj0Q+P93F7MONkciOa64sUom70PoVPCq1HwdALXhVsi IIxlyv4V/6PJsmHLSGSBY0jGUzq3ENkm2/6W4Y+vmfEU2lFSrEf5SrunnbmEXG4GsIj2 U1drhzs5PHQn1v/rSywO5khAtoXfI/wbUaAxWoWqMiTqAGFEUTAw40N7ynnmxigQuhPx d4mIGW69OubAktTVrS3PErWyLdxXLkeEQyqPp2AMaUwNiRcmsx9zbLy/WAUD0GX+uigu S4y4XC6sJIBu2wTz/oG8pgd/3Urbcv4Iu1ot3kjwdYvxj9f5NuxTq45g9AqDMUILe0j6 4YJQ== X-Gm-Message-State: APzg51D9sLgY0ipbZ8g6GEcmy6tynDB/ipCOt/EGtOAcLP4TnvKIuhHT Gl7fCDzZLC5Yb/NaBh5wZ4F9TdH5/CQ= X-Google-Smtp-Source: ANB0VdZGGOaAAK2BOHjX24W2IWVESLu3CLiXEjgFf5lmGynwiaO2dzGFIH+FdtQsH8OMGD4ALtBsng== X-Received: by 2002:adf:eb87:: with SMTP id t7-v6mr26955315wrn.123.1536157359033; Wed, 05 Sep 2018 07:22:39 -0700 (PDT) Received: from localhost.localdomain ([95.144.165.37]) by smtp.gmail.com with ESMTPSA id x125-v6sm2851438wmg.27.2018.09.05.07.22.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Sep 2018 07:22:38 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Wed, 5 Sep 2018 15:22:22 +0100 Message-Id: <20180905142222.3251-8-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180905142222.3251-1-tvrtko.ursulin@linux.intel.com> References: <20180905142222.3251-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH 7/7] drm/i915/icl: Support co-existance between per-context SSEU and OA X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin When OA is active we want to lock the powergating configuration, but on Icelake users like media stack will have issues if we lock to the full device configuration. Instead lock to a subset of (sub)slices which are currently a known working configuration for all users. Signed-off-by: Tvrtko Ursulin Cc: Lionel Landwerlin --- drivers/gpu/drm/i915/intel_lrc.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 3c85392a3109..19c9c46308e5 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2502,13 +2502,28 @@ u32 gen8_make_rpcs(struct drm_i915_private *dev_priv, /* * If i915/perf is active, we want a stable powergating configuration - * on the system. The most natural configuration to take in that case - * is the default (i.e maximum the hardware can do). + * on the system. + * + * We could choose full enablement, but on ICL we know there are use + * cases which disable slices for functional, apart for performance + * reasons. So in this case we select a known stable subset. */ - if (unlikely(dev_priv->perf.oa.exclusive_stream)) - ctx_sseu = intel_device_default_sseu(dev_priv); - else + if (!dev_priv->perf.oa.exclusive_stream) { ctx_sseu = *req_sseu; + } else { + ctx_sseu = intel_device_default_sseu(dev_priv); + + if (IS_GEN11(dev_priv)) { + /* + * We only need subslice count so it doesn't matter + * which ones we select - just turn of low bits in the + * amount of half of all available subslices per slice. + */ + ctx_sseu.subslice_mask = + ~(~0 << (hweight8(ctx_sseu.subslice_mask) / 2)); + ctx_sseu.slice_mask = 0x1; + } + } slices = hweight8(ctx_sseu.slice_mask); subslices = hweight8(ctx_sseu.subslice_mask);