diff mbox series

[1/4] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake

Message ID 20180913212251.22283-1-jose.souza@intel.com (mailing list archive)
State New, archived
Headers show
Series [1/4] drm/i915/runtime_pm: Share code to enable/disable PCH reset handshake | expand

Commit Message

Souza, Jose Sept. 13, 2018, 9:22 p.m. UTC 
Instead of have the same code spread into 4 platforms lets share it.
BXT do not have a PCH so here also handling this case by unseting
RESET_PCH_HANDSHAKE_ENABLE.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 29 ++++++++++++++-----------
 1 file changed, 16 insertions(+), 13 deletions(-)

Comments

Rodrigo Vivi Sept. 13, 2018, 9:41 p.m. UTC | #1 
On Thu, Sep 13, 2018 at 02:22:48PM -0700, José Roberto de Souza wrote:
> Instead of have the same code spread into 4 platforms lets share it.
> BXT do not have a PCH so here also handling this case by unseting
> RESET_PCH_HANDSHAKE_ENABLE.
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 29 ++++++++++++++-----------
>  1 file changed, 16 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 480dadb1047b..8bcb33367d0d 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3239,18 +3239,28 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
>  	I915_WRITE(MBUS_ABOX_CTL, val);
>  }
>  
> +static void skl_pch_reset_handshake(struct drm_i915_private *dev_priv)
> +{
> +	u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
> +
> +	if (HAS_PCH_SPLIT(dev_priv))
> +		val |= RESET_PCH_HANDSHAKE_ENABLE;
> +	else
> +		val &= ~RESET_PCH_HANDSHAKE_ENABLE;
> +
> +	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> +}
> +
>  static void skl_display_core_init(struct drm_i915_private *dev_priv,
>  				   bool resume)
>  {
>  	struct i915_power_domains *power_domains = &dev_priv->power_domains;
>  	struct i915_power_well *well;
> -	uint32_t val;
>  
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
>  	/* enable PCH reset handshake */
> -	val = I915_READ(HSW_NDE_RSTWRN_OPT);
> -	I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
> +	skl_pch_reset_handshake(dev_priv);
>  
>  	/* enable PG1 and Misc I/O */
>  	mutex_lock(&power_domains->lock);
> @@ -3306,7 +3316,6 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
>  {
>  	struct i915_power_domains *power_domains = &dev_priv->power_domains;
>  	struct i915_power_well *well;
> -	uint32_t val;
>  
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
> @@ -3316,9 +3325,7 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
>  	 * Move the handshake programming to initialization sequence.
>  	 * Previously was left up to BIOS.

I think after this change this comment here gets far from the code
so it is not clear why when PCH not present you unset.

so maybe we should move with this patch, but only with the setting
path and leave this here as is since it seems a workaround exclusive
for bxt... 

>  	 */
> -	val = I915_READ(HSW_NDE_RSTWRN_OPT);
> -	val &= ~RESET_PCH_HANDSHAKE_ENABLE;
> -	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> +	skl_pch_reset_handshake(dev_priv);
>  
>  	/* Enable PG1 */
>  	mutex_lock(&power_domains->lock);
> @@ -3439,9 +3446,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
>  	/* 1. Enable PCH Reset Handshake */
> -	val = I915_READ(HSW_NDE_RSTWRN_OPT);
> -	val |= RESET_PCH_HANDSHAKE_ENABLE;
> -	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> +	skl_pch_reset_handshake(dev_priv);
>  
>  	/* 2. Enable Comp */
>  	val = I915_READ(CHICKEN_MISC_2);
> @@ -3524,9 +3529,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
>  	/* 1. Enable PCH reset handshake. */
> -	val = I915_READ(HSW_NDE_RSTWRN_OPT);
> -	val |= RESET_PCH_HANDSHAKE_ENABLE;
> -	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> +	skl_pch_reset_handshake(dev_priv);
>  
>  	for (port = PORT_A; port <= PORT_B; port++) {
>  		/* 2. Enable DDI combo PHY comp. */
> -- 
> 2.19.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Ville Syrjälä Sept. 14, 2018, 12:17 p.m. UTC | #2 
On Thu, Sep 13, 2018 at 02:22:48PM -0700, José Roberto de Souza wrote:
> Instead of have the same code spread into 4 platforms lets share it.
> BXT do not have a PCH so here also handling this case by unseting
> RESET_PCH_HANDSHAKE_ENABLE.
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 29 ++++++++++++++-----------
>  1 file changed, 16 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 480dadb1047b..8bcb33367d0d 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3239,18 +3239,28 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
>  	I915_WRITE(MBUS_ABOX_CTL, val);
>  }
>  
> +static void skl_pch_reset_handshake(struct drm_i915_private *dev_priv)
> +{
> +	u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
> +
> +	if (HAS_PCH_SPLIT(dev_priv))
> +		val |= RESET_PCH_HANDSHAKE_ENABLE;
> +	else
> +		val &= ~RESET_PCH_HANDSHAKE_ENABLE;
> +
> +	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> +}

hsw has this too. And ivb has a slightly different version. Could unify
it all. And maybe pass the enable/disable as a paramter to make it clear
from reading the calling code what it's doing?

> +
>  static void skl_display_core_init(struct drm_i915_private *dev_priv,
>  				   bool resume)
>  {
>  	struct i915_power_domains *power_domains = &dev_priv->power_domains;
>  	struct i915_power_well *well;
> -	uint32_t val;
>  
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
>  	/* enable PCH reset handshake */
> -	val = I915_READ(HSW_NDE_RSTWRN_OPT);
> -	I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
> +	skl_pch_reset_handshake(dev_priv);
>  
>  	/* enable PG1 and Misc I/O */
>  	mutex_lock(&power_domains->lock);
> @@ -3306,7 +3316,6 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
>  {
>  	struct i915_power_domains *power_domains = &dev_priv->power_domains;
>  	struct i915_power_well *well;
> -	uint32_t val;
>  
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
> @@ -3316,9 +3325,7 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
>  	 * Move the handshake programming to initialization sequence.
>  	 * Previously was left up to BIOS.
>  	 */
> -	val = I915_READ(HSW_NDE_RSTWRN_OPT);
> -	val &= ~RESET_PCH_HANDSHAKE_ENABLE;
> -	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> +	skl_pch_reset_handshake(dev_priv);
>  
>  	/* Enable PG1 */
>  	mutex_lock(&power_domains->lock);
> @@ -3439,9 +3446,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
>  	/* 1. Enable PCH Reset Handshake */
> -	val = I915_READ(HSW_NDE_RSTWRN_OPT);
> -	val |= RESET_PCH_HANDSHAKE_ENABLE;
> -	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> +	skl_pch_reset_handshake(dev_priv);
>  
>  	/* 2. Enable Comp */
>  	val = I915_READ(CHICKEN_MISC_2);
> @@ -3524,9 +3529,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
>  	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
>  	/* 1. Enable PCH reset handshake. */
> -	val = I915_READ(HSW_NDE_RSTWRN_OPT);
> -	val |= RESET_PCH_HANDSHAKE_ENABLE;
> -	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> +	skl_pch_reset_handshake(dev_priv);
>  
>  	for (port = PORT_A; port <= PORT_B; port++) {
>  		/* 2. Enable DDI combo PHY comp. */
> -- 
> 2.19.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 480dadb1047b..8bcb33367d0d 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3239,18 +3239,28 @@  static void icl_mbus_init(struct drm_i915_private *dev_priv)
 	I915_WRITE(MBUS_ABOX_CTL, val);
 }
 
+static void skl_pch_reset_handshake(struct drm_i915_private *dev_priv)
+{
+	u32 val = I915_READ(HSW_NDE_RSTWRN_OPT);
+
+	if (HAS_PCH_SPLIT(dev_priv))
+		val |= RESET_PCH_HANDSHAKE_ENABLE;
+	else
+		val &= ~RESET_PCH_HANDSHAKE_ENABLE;
+
+	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+}
+
 static void skl_display_core_init(struct drm_i915_private *dev_priv,
 				   bool resume)
 {
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *well;
-	uint32_t val;
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
 	/* enable PCH reset handshake */
-	val = I915_READ(HSW_NDE_RSTWRN_OPT);
-	I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
+	skl_pch_reset_handshake(dev_priv);
 
 	/* enable PG1 and Misc I/O */
 	mutex_lock(&power_domains->lock);
@@ -3306,7 +3316,6 @@  void bxt_display_core_init(struct drm_i915_private *dev_priv,
 {
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *well;
-	uint32_t val;
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
@@ -3316,9 +3325,7 @@  void bxt_display_core_init(struct drm_i915_private *dev_priv,
 	 * Move the handshake programming to initialization sequence.
 	 * Previously was left up to BIOS.
 	 */
-	val = I915_READ(HSW_NDE_RSTWRN_OPT);
-	val &= ~RESET_PCH_HANDSHAKE_ENABLE;
-	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+	skl_pch_reset_handshake(dev_priv);
 
 	/* Enable PG1 */
 	mutex_lock(&power_domains->lock);
@@ -3439,9 +3446,7 @@  static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
 	/* 1. Enable PCH Reset Handshake */
-	val = I915_READ(HSW_NDE_RSTWRN_OPT);
-	val |= RESET_PCH_HANDSHAKE_ENABLE;
-	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+	skl_pch_reset_handshake(dev_priv);
 
 	/* 2. Enable Comp */
 	val = I915_READ(CHICKEN_MISC_2);
@@ -3524,9 +3529,7 @@  static void icl_display_core_init(struct drm_i915_private *dev_priv,
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
 	/* 1. Enable PCH reset handshake. */
-	val = I915_READ(HSW_NDE_RSTWRN_OPT);
-	val |= RESET_PCH_HANDSHAKE_ENABLE;
-	I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
+	skl_pch_reset_handshake(dev_priv);
 
 	for (port = PORT_A; port <= PORT_B; port++) {
 		/* 2. Enable DDI combo PHY comp. */