diff mbox series

[CI,2/3] drm/i915: Check engine->default_state mapping on module load

Message ID 20180914123504.2062-2-chris@chris-wilson.co.uk (mailing list archive)
State New, archived
Headers show
Series [CI,1/3] drm/i915/execlists: Delay updating ring register state after resume | expand

Commit Message

Chris Wilson Sept. 14, 2018, 12:35 p.m. UTC 
Check we can indeed acquire a WB mapping of the context image on module
load. Later this will give us the opportunity to validate that we can
switch from WC to WB as required.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 11 +++++++++++
 1 file changed, 11 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 89834ce19acd..d276fb302d4e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5416,6 +5416,7 @@  static int __intel_engines_record_defaults(struct drm_i915_private *i915)
 
 	for_each_engine(engine, i915, id) {
 		struct i915_vma *state;
+		void *vaddr;
 
 		state = to_intel_context(ctx, engine)->state;
 		if (!state)
@@ -5438,6 +5439,16 @@  static int __intel_engines_record_defaults(struct drm_i915_private *i915)
 			goto err_active;
 
 		engine->default_state = i915_gem_object_get(state->obj);
+
+		/* Check we can acquire the image of the context state */
+		vaddr = i915_gem_object_pin_map(engine->default_state,
+						I915_MAP_WB);
+		if (IS_ERR(vaddr)) {
+			err = PTR_ERR(vaddr);
+			goto err_active;
+		}
+
+		i915_gem_object_unpin_map(engine->default_state);
 	}
 
 	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {