From patchwork Fri Sep 14 16:09:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10601001 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4303615E8 for ; Fri, 14 Sep 2018 16:09:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2AC612BB06 for ; Fri, 14 Sep 2018 16:09:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1F54D2BB30; Fri, 14 Sep 2018 16:09:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CD4C72BB06 for ; Fri, 14 Sep 2018 16:09:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1764F6E93E; Fri, 14 Sep 2018 16:09:49 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2251E6E93E for ; Fri, 14 Sep 2018 16:09:46 +0000 (UTC) Received: by mail-wm1-x341.google.com with SMTP id y2-v6so2497851wma.1 for ; Fri, 14 Sep 2018 09:09:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EQtOo3I/PIzGR+AdPIHMARRUHKv9IzHAwiJC03NaQO4=; b=j/RTb8Vypr/6QxTJkbjswd39JClhs6nu1aFi2Bajw/v0S1ZtFKELtLAApe/ht1Atnr +FlNlGEkmxkRRb1luBShOMPMORMG2ma5aMNpqS/Cn7Fq0y+eiy+WwqxwTl/HoxnbHsTk aNBI6dUEITji/RZBDz0QDpDUoBLdoKpXx6fhifmQI8rOXcng9lpFrnKwMQ+wD7sm7OLE eu7kEaPfF4Dzf7iuZ0b9HVA/iMGdphkVi66g4rGgM8Ln7IhBdJ4XDbr8m99HbPcbYeN6 LgKWgwkW4/GaeJf56OY68I0bdiNVQggXH4UozWYU6DJbbtNN6F0N6+X+NmreqBNsM80J dAWA== X-Gm-Message-State: APzg51B18izC4Hv60UKaLu4IgL3b63RjeP1DVLCaVUpK16CcWGqHfAW8 ExJ+0u3YC2Q1D/02jhnCBpJ0Zd6C4rY= X-Google-Smtp-Source: ANB0VdYvKxaK72ZCopsOCokOYEGeFD+b/uMUI2cGrgdem6J+yfZ5XBMlpwKqQg3uIi0uEaoqssUg/A== X-Received: by 2002:a1c:1d87:: with SMTP id d129-v6mr2937520wmd.34.1536941384597; Fri, 14 Sep 2018 09:09:44 -0700 (PDT) Received: from localhost.localdomain ([95.144.165.37]) by smtp.gmail.com with ESMTPSA id z141-v6sm2651536wmc.3.2018.09.14.09.09.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Sep 2018 09:09:44 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Fri, 14 Sep 2018 17:09:32 +0100 Message-Id: <20180914160932.16457-7-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180914160932.16457-1-tvrtko.ursulin@linux.intel.com> References: <20180914160932.16457-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH 6/6] drm/i915/icl: Support co-existance between per-context SSEU and OA X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin When OA is active we want to lock the powergating configuration, but on Icelake users like media stack will have issues if we lock to the full device configuration. Instead lock to a subset of (sub)slices which are currently a known working configuration for all users. Signed-off-by: Tvrtko Ursulin Cc: Lionel Landwerlin --- drivers/gpu/drm/i915/intel_lrc.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 0cfa99a13522..2aaf2237a2b0 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2522,13 +2522,28 @@ u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *req_sseu) /* * If i915/perf is active, we want a stable powergating configuration - * on the system. The most natural configuration to take in that case - * is the default (i.e maximum the hardware can do). + * on the system. + * + * We could choose full enablement, but on ICL we know there are use + * cases which disable slices for functional, apart for performance + * reasons. So in this case we select a known stable subset. */ - if (unlikely(i915->perf.oa.exclusive_stream)) - ctx_sseu = intel_device_default_sseu(i915); - else + if (!i915->perf.oa.exclusive_stream) { ctx_sseu = *req_sseu; + } else { + ctx_sseu = intel_device_default_sseu(i915); + + if (IS_GEN11(i915)) { + /* + * We only need subslice count so it doesn't matter + * which ones we select - just turn of low bits in the + * amount of half of all available subslices per slice. + */ + ctx_sseu.subslice_mask = + ~(~0 << (hweight8(ctx_sseu.subslice_mask) / 2)); + ctx_sseu.slice_mask = 0x1; + } + } slices = hweight8(ctx_sseu.slice_mask); subslices = hweight8(ctx_sseu.subslice_mask);