From patchwork Mon Sep 17 11:30:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10602577 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ED1721508 for ; Mon, 17 Sep 2018 11:31:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D6A552992D for ; Mon, 17 Sep 2018 11:31:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D527A2998B; Mon, 17 Sep 2018 11:31:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8EF5829979 for ; Mon, 17 Sep 2018 11:31:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D86446E26C; Mon, 17 Sep 2018 11:31:17 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by gabe.freedesktop.org (Postfix) with ESMTPS id 311F06E261 for ; Mon, 17 Sep 2018 11:31:12 +0000 (UTC) Received: by mail-wm1-x341.google.com with SMTP id s12-v6so9168562wmc.0 for ; Mon, 17 Sep 2018 04:31:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ntQ28b0jePfbe6gAToX6Qj1zorRWhxbCP4PyytLAxmQ=; b=kbN8XyETzIjPktAM/qNhJUsSQJSpp6Qy0KWuaL43NAmQoinja+gA2BGTdpkvFsOjEF t4pEQQsjLe9rJLxRbJkdFKZafKVs9v1eMkw02e79L8UTA3xW/+ddDflUQWqmBnMRAhhw dACqpxjiC56FKq3E01zeo6AJSv2/yedc0AcZOuYyFrElaF//hdD8py+RRcH3hi5ASMyK hchqbu4aotfU9lHeA5aHmzOUY4XuLNgh59XtLBBP66gRDvvVF6uxL03jT4r9P7QTZzPR EHHP3Ci8jtZksnFEKkJASKn58AwFHroVLu4RrIXoeaq7qN1pnwJHn3NJLvYzQIvJjWhh hcWA== X-Gm-Message-State: APzg51Ay5hr5N3mwuyugjVdfckA/W1dtKkl55e+lBCmx+YyZDONhIlCD Km/LBM8j6S4bBKIaL7Dvy/U1JEe4Oqc= X-Google-Smtp-Source: ANB0VdbXpPTiUaBoWvmJ7r+ZxF3LE/4lV7Qc7el4EJNBGwfcxGJFhDygTQp5bfClZRL73x5yjUBJuw== X-Received: by 2002:a7b:c18a:: with SMTP id y10-v6mr11495031wmi.87.1537183870599; Mon, 17 Sep 2018 04:31:10 -0700 (PDT) Received: from localhost.localdomain ([95.144.165.37]) by smtp.gmail.com with ESMTPSA id o3-v6sm10781971wrn.58.2018.09.17.04.31.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Sep 2018 04:31:09 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Mon, 17 Sep 2018 12:30:58 +0100 Message-Id: <20180917113058.28994-7-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180917113058.28994-1-tvrtko.ursulin@linux.intel.com> References: <20180917113058.28994-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH 6/6] drm/i915/icl: Support co-existence between per-context SSEU and OA X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin When OA is active we want to lock the powergating configuration, but on Icelake, users like the media stack will have issues if we lock to the full device configuration. Instead lock to a subset of (sub)slices which are currently a known working configuration for all users. v2: * Fix commit message spelling. Signed-off-by: Tvrtko Ursulin Cc: Lionel Landwerlin Reviewed-by: Lionel Landwerlin --- drivers/gpu/drm/i915/intel_lrc.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index b5603e977a3f..cded1f1d9ec2 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2521,13 +2521,28 @@ u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *req_sseu) /* * If i915/perf is active, we want a stable powergating configuration - * on the system. The most natural configuration to take in that case - * is the default (i.e maximum the hardware can do). + * on the system. + * + * We could choose full enablement, but on ICL we know there are use + * cases which disable slices for functional, apart for performance + * reasons. So in this case we select a known stable subset. */ - if (unlikely(i915->perf.oa.exclusive_stream)) - ctx_sseu = intel_device_default_sseu(i915); - else + if (!i915->perf.oa.exclusive_stream) { ctx_sseu = *req_sseu; + } else { + ctx_sseu = intel_device_default_sseu(i915); + + if (IS_GEN11(i915)) { + /* + * We only need subslice count so it doesn't matter + * which ones we select - just turn of low bits in the + * amount of half of all available subslices per slice. + */ + ctx_sseu.subslice_mask = + ~(~0 << (hweight8(ctx_sseu.subslice_mask) / 2)); + ctx_sseu.slice_mask = 0x1; + } + } slices = hweight8(ctx_sseu.slice_mask); subslices = hweight8(ctx_sseu.subslice_mask);