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[1/8] drm/i915/psr: Share PSR and PSR2 exit mask

Message ID 20180920204327.3513-1-jose.souza@intel.com (mailing list archive)
State New, archived
Headers show
Series [1/8] drm/i915/psr: Share PSR and PSR2 exit mask | expand

Commit Message

Souza, Jose Sept. 20, 2018, 8:43 p.m. UTC
Now both PSR and PSR2 have the same exit mask, so let's share then
instead of have the same code 2 times.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 34 ++++++++++++--------------------
 1 file changed, 13 insertions(+), 21 deletions(-)

Comments

Dhinakaran Pandiyan Sept. 25, 2018, 12:06 a.m. UTC | #1
On Thursday, September 20, 2018 1:43:20 PM PDT José Roberto de Souza wrote:
> Now both PSR and PSR2 have the same exit mask, so let's share then
> instead of have the same code 2 times.
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 34 ++++++++++++--------------------
>  1 file changed, 13 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c index b6838b525502..358bbcd3b5f3 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -575,28 +575,20 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp, else
>  			chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
>  		I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
> -
> -		I915_WRITE(EDP_PSR_DEBUG,
> -			   EDP_PSR_DEBUG_MASK_MEMUP |
> -			   EDP_PSR_DEBUG_MASK_HPD |
> -			   EDP_PSR_DEBUG_MASK_LPSP |
> -			   EDP_PSR_DEBUG_MASK_MAX_SLEEP |
> -			   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
> -	} else {
> -		/*
> -		 * Per Spec: Avoid continuous PSR exit by masking MEMUP
> -		 * and HPD. also mask LPSP to avoid dependency on other
> -		 * drivers that might block runtime_pm besides
> -		 * preventing  other hw tracking issues now we can rely
> -		 * on frontbuffer tracking.
> -		 */
> -		I915_WRITE(EDP_PSR_DEBUG,
> -			   EDP_PSR_DEBUG_MASK_MEMUP |
> -			   EDP_PSR_DEBUG_MASK_HPD |
> -			   EDP_PSR_DEBUG_MASK_LPSP |
> -			   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
> -			   EDP_PSR_DEBUG_MASK_MAX_SLEEP);
>  	}
> +
> +	/*
> +	 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
> +	 * mask LPSP to avoid dependency on other drivers that might block
> +	 * runtime_pm besides preventing  other hw tracking issues now we
> +	 * can rely on frontbuffer tracking.
> +	 */

Hmm.. I don't think I understand this comment completely and we should update 
it. This patch however looks correct,
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>


> +	I915_WRITE(EDP_PSR_DEBUG,
> +		   EDP_PSR_DEBUG_MASK_MEMUP |
> +		   EDP_PSR_DEBUG_MASK_HPD |
> +		   EDP_PSR_DEBUG_MASK_LPSP |
> +		   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
> +		   EDP_PSR_DEBUG_MASK_MAX_SLEEP);
>  }
> 
>  static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b6838b525502..358bbcd3b5f3 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -575,28 +575,20 @@  static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		else
 			chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
 		I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
-
-		I915_WRITE(EDP_PSR_DEBUG,
-			   EDP_PSR_DEBUG_MASK_MEMUP |
-			   EDP_PSR_DEBUG_MASK_HPD |
-			   EDP_PSR_DEBUG_MASK_LPSP |
-			   EDP_PSR_DEBUG_MASK_MAX_SLEEP |
-			   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
-	} else {
-		/*
-		 * Per Spec: Avoid continuous PSR exit by masking MEMUP
-		 * and HPD. also mask LPSP to avoid dependency on other
-		 * drivers that might block runtime_pm besides
-		 * preventing  other hw tracking issues now we can rely
-		 * on frontbuffer tracking.
-		 */
-		I915_WRITE(EDP_PSR_DEBUG,
-			   EDP_PSR_DEBUG_MASK_MEMUP |
-			   EDP_PSR_DEBUG_MASK_HPD |
-			   EDP_PSR_DEBUG_MASK_LPSP |
-			   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
-			   EDP_PSR_DEBUG_MASK_MAX_SLEEP);
 	}
+
+	/*
+	 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
+	 * mask LPSP to avoid dependency on other drivers that might block
+	 * runtime_pm besides preventing  other hw tracking issues now we
+	 * can rely on frontbuffer tracking.
+	 */
+	I915_WRITE(EDP_PSR_DEBUG,
+		   EDP_PSR_DEBUG_MASK_MEMUP |
+		   EDP_PSR_DEBUG_MASK_HPD |
+		   EDP_PSR_DEBUG_MASK_LPSP |
+		   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
+		   EDP_PSR_DEBUG_MASK_MAX_SLEEP);
 }
 
 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,