| Message ID | 20180920204327.3513-3-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/8] drm/i915/psr: Share PSR and PSR2 exit mask | expand |
On Thu, 2018-09-20 at 13:43 -0700, José Roberto de Souza wrote: > eDP spec states 2 different bits to enable sink to trigger a > interruption when there is a CRC mismatch. > DP_PSR_CRC_VERIFICATION is for PSR only and > DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only. > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/intel_psr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > b/drivers/gpu/drm/i915/intel_psr.c > index 6f3c6f0c539f..b4edbbda8d71 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -340,7 +340,7 @@ static void intel_psr_enable_sink(struct intel_dp > *intel_dp) > if (dev_priv->psr.psr2_enabled) { > drm_dp_dpcd_writeb(&intel_dp->aux, > DP_RECEIVER_ALPM_CONFIG, > DP_ALPM_ENABLE); > - dpcd_val |= DP_PSR_ENABLE_PSR2; > + dpcd_val |= DP_PSR_ENABLE_PSR2 | > DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; > } } else if (INTEL_GEN(dev_priv) >=8) { dpcd_val |= DP_PSR_CRC_VERIFICATION; } How about doing this for clarity? > > if (dev_priv->psr.link_standby)
On Tue, 2018-09-25 at 00:28 +0000, Pandiyan, Dhinakaran wrote: > On Thu, 2018-09-20 at 13:43 -0700, José Roberto de Souza wrote: > > eDP spec states 2 different bits to enable sink to trigger a > > interruption when there is a CRC mismatch. > > DP_PSR_CRC_VERIFICATION is for PSR only and > > DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only. Do you have a system that triggers a short pulse for this? If yes, do we end up calling the PSR error interrupt handler at all? intel_dp_short_pulse() ... if intel_dp_needs_link_retrain() return intel_psr_short_pulse() > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > --- > > drivers/gpu/drm/i915/intel_psr.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > index 6f3c6f0c539f..b4edbbda8d71 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -340,7 +340,7 @@ static void intel_psr_enable_sink(struct > > intel_dp > > *intel_dp) > > if (dev_priv->psr.psr2_enabled) { > > drm_dp_dpcd_writeb(&intel_dp->aux, > > DP_RECEIVER_ALPM_CONFIG, > > DP_ALPM_ENABLE); > > - dpcd_val |= DP_PSR_ENABLE_PSR2; > > + dpcd_val |= DP_PSR_ENABLE_PSR2 | > > DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; > > } > > } else if (INTEL_GEN(dev_priv) >=8) { > > dpcd_val |= DP_PSR_CRC_VERIFICATION; > } > > How about doing this for clarity? > > > > > > > if (dev_priv->psr.link_standby) > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 6f3c6f0c539f..b4edbbda8d71 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -340,7 +340,7 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp) if (dev_priv->psr.psr2_enabled) { drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, DP_ALPM_ENABLE); - dpcd_val |= DP_PSR_ENABLE_PSR2; + dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; } if (dev_priv->psr.link_standby)
eDP spec states 2 different bits to enable sink to trigger a interruption when there is a CRC mismatch. DP_PSR_CRC_VERIFICATION is for PSR only and DP_PSR_IRQ_HPD_WITH_CRC_ERRORS is for PSR2 only. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/intel_psr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)