From patchwork Wed Oct 3 12:03:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10624701 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C723A13BB for ; Wed, 3 Oct 2018 12:04:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BB06728944 for ; Wed, 3 Oct 2018 12:04:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AEFFE28984; Wed, 3 Oct 2018 12:04:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5CE9928944 for ; Wed, 3 Oct 2018 12:04:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D26946E456; Wed, 3 Oct 2018 12:04:17 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by gabe.freedesktop.org (Postfix) with ESMTPS id A0ADE6E454 for ; Wed, 3 Oct 2018 12:04:14 +0000 (UTC) Received: by mail-wm1-x344.google.com with SMTP id s12-v6so5463848wmc.0 for ; Wed, 03 Oct 2018 05:04:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XRJajo83SD6DOPiFE9+uLj+fU0ay/WOrHNexi/p1zqM=; b=WO9QcQQ/eoQ7wJOqfLLvE+GyGLg4/tGFUajt9u8RdFGsmRFID3Jq3IHU5tau5CYkjO 3Ggv8QJD7Vmh5Tm9gnR/74ETivg8/8Z/CTFpKOVjVRBDucG4qlPyVkzLHVvQqjPBif6i wK6ArAifpP0EozbAeTw7AOzTUPl4GghLLEd0ZwKaflQ5a/S2PyynIrahSYEHBAsS8E4Z P68056nL4swrKG/ukKCHw30aMwujuip1PrNdLTlD3K/E/aKws2SW3a1bC1lhrRbO/BpU ZWpFaevFvp9mPbjzFDRTo6HxSYvGB2zd9XTrW02UxpwDGvpy8OFB6mn79f9+eU4cGO4C 4U2Q== X-Gm-Message-State: ABuFfogn8SORq52o7aDy/GU9Hhbm6CwXIiiZ5sM5yHZR6pR++3TxfQJ+ xfLBl65UYWf81BedSfcHD/K96iU/50M= X-Google-Smtp-Source: ACcGV60ve2mXJ0vaac4/R1m4jCQZxjChAC/M09p0F7MkDNpdMdXUon8zjMihGbcNGRu6B21HyFrZfQ== X-Received: by 2002:a1c:9295:: with SMTP id u143-v6mr1219741wmd.126.1538568253074; Wed, 03 Oct 2018 05:04:13 -0700 (PDT) Received: from localhost.localdomain ([95.144.165.37]) by smtp.gmail.com with ESMTPSA id f69-v6sm866657wmf.34.2018.10.03.05.04.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Oct 2018 05:04:12 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Wed, 3 Oct 2018 13:03:54 +0100 Message-Id: <20181003120406.6784-2-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181003120406.6784-1-tvrtko.ursulin@linux.intel.com> References: <20181003120406.6784-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [RFC 01/13] drm/i915/pmu: Fix enable count array size and bounds checking X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Enable count array is supposed to have one counter for each possible engine sampler. As such array sizing and bounds checking is not correct when more engine samplers are added. At the same time tidy the assert for readability and robustness. Signed-off-by: Tvrtko Ursulin Fixes: b46a33e271ed ("drm/i915/pmu: Expose a PMU interface for perf queries") Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_pmu.c | 13 +++++++++---- drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index d6c8f8fdfda5..417fda7208be 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -594,7 +594,8 @@ static void i915_pmu_enable(struct perf_event *event) * Update the bitmask of enabled events and increment * the event reference counter. */ - GEM_BUG_ON(bit >= I915_PMU_MASK_BITS); + BUILD_BUG_ON(ARRAY_SIZE(i915->pmu.enable_count) != I915_PMU_MASK_BITS); + GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count)); GEM_BUG_ON(i915->pmu.enable_count[bit] == ~0); i915->pmu.enable |= BIT_ULL(bit); i915->pmu.enable_count[bit]++; @@ -618,7 +619,10 @@ static void i915_pmu_enable(struct perf_event *event) GEM_BUG_ON(!engine); engine->pmu.enable |= BIT(sample); - GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS); + BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) != + (1 << I915_PMU_SAMPLE_BITS)); + GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count)); + GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample)); GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0); engine->pmu.enable_count[sample]++; } @@ -650,7 +654,8 @@ static void i915_pmu_disable(struct perf_event *event) engine_event_class(event), engine_event_instance(event)); GEM_BUG_ON(!engine); - GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS); + GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count)); + GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample)); GEM_BUG_ON(engine->pmu.enable_count[sample] == 0); /* * Decrement the reference count and clear the enabled @@ -660,7 +665,7 @@ static void i915_pmu_disable(struct perf_event *event) engine->pmu.enable &= ~BIT(sample); } - GEM_BUG_ON(bit >= I915_PMU_MASK_BITS); + GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count)); GEM_BUG_ON(i915->pmu.enable_count[bit] == 0); /* * Decrement the reference count and clear the enabled diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index f6ec48a75a69..7078132fc631 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -432,7 +432,7 @@ struct intel_engine_cs { * * Index number corresponds to the bit number from @enable. */ - unsigned int enable_count[I915_PMU_SAMPLE_BITS]; + unsigned int enable_count[1 << I915_PMU_SAMPLE_BITS]; /** * @sample: Counter values for sampling events. *