From patchwork Wed Oct 3 12:03:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10624707 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B96C913BB for ; Wed, 3 Oct 2018 12:04:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AB2B828944 for ; Wed, 3 Oct 2018 12:04:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9F76E28952; Wed, 3 Oct 2018 12:04:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 33BAB28944 for ; Wed, 3 Oct 2018 12:04:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5C1CE6E454; Wed, 3 Oct 2018 12:04:28 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by gabe.freedesktop.org (Postfix) with ESMTPS id 81B676E455 for ; Wed, 3 Oct 2018 12:04:15 +0000 (UTC) Received: by mail-wr1-x444.google.com with SMTP id n1-v6so5825321wrt.10 for ; Wed, 03 Oct 2018 05:04:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3VncU3YH7xau4FEChOJPsccTZvYLzOnIO8dTxXFJLxI=; b=p3lWmN4P7N7UvWsaXYjvkml5p7IV+8l3tQ1rmspRFxa7Eihom3ScbtjvD/80pZvoAT /oozTCMvJmf8Mbx92nos1lv3//rf+P3lcUgRXxvIYYDuLs44Ho3bCaCYhEQfjSJNK/WI 85V0o1QSEKSPDSmnQP9Xlq+i3sxe5tXX6HkPY5EI3X3iunS1XpaVTfYDU/gpXKO7Uyu5 b78yd+wS/0xrkImeuEObMED0SE5YJDBIgm6dEILV/pl9vENRC9H52iD7+4nHwW0SSGeN LtBvuJdi2xt6xbKrSaZ6Aj30raenql2htoufz127dZ0Tgp6WGXC/eO0MiSjrKO14KeFS zXXQ== X-Gm-Message-State: ABuFfoh8qXe/LQnbOV+QuHbrTz1ciEKBtbQGlu2EDr5qNvJCL2uCqUT9 IVrf5TR4Uphx3EJhdu0dIvOQlDavJkA= X-Google-Smtp-Source: ACcGV60qqon02RA+aX0q1U8sW443hVxuaa5im3bkBoAnPKqO1uy423SK4QSJvQ7xg7vRKuXhfyOhSQ== X-Received: by 2002:a5d:6b92:: with SMTP id n18-v6mr931999wrx.295.1538568253927; Wed, 03 Oct 2018 05:04:13 -0700 (PDT) Received: from localhost.localdomain ([95.144.165.37]) by smtp.gmail.com with ESMTPSA id f69-v6sm866657wmf.34.2018.10.03.05.04.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Oct 2018 05:04:13 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Wed, 3 Oct 2018 13:03:55 +0100 Message-Id: <20181003120406.6784-3-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181003120406.6784-1-tvrtko.ursulin@linux.intel.com> References: <20181003120406.6784-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [RFC 02/13] drm/i915: Keep a count of requests waiting for a slot on GPU X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Keep a per-engine number of runnable (waiting for GPU time) requests. We choose to mange the runnable counter at the backend level instead of at the request submit_notify callback. The latter would be more consolidated and less code, but it would require making the counter either atomic_t or taking the engine->timeline->lock in submit_notify. So the choice is to do it at the backend level for the benefit of fewer atomic instructions. v2: * Move queued increment from insert_request to execlist_submit_request to avoid bumping when re-ordering for priority. * Support the counter on the ringbuffer submission path as well, albeit just notionally. (Chris Wilson) v3: * Rebase. v4: * Rename and move the stats into a container structure. (Chris Wilson) v5: * Re-order fields in struct intel_engine_cs. (Chris Wilson) v6-v8: * Rebases. v9: * Fix accounting during wedging. v10: * Improved commit message. (Chris Wilson) Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_gem.c | 1 + drivers/gpu/drm/i915/i915_request.c | 7 +++++++ drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++-- drivers/gpu/drm/i915/intel_lrc.c | 1 + drivers/gpu/drm/i915/intel_ringbuffer.h | 9 +++++++++ 5 files changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 7d45e71100bc..d3a730f6ef65 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3309,6 +3309,7 @@ static void nop_complete_submit_request(struct i915_request *request) dma_fence_set_error(&request->fence, -EIO); spin_lock_irqsave(&request->engine->timeline.lock, flags); + request->engine->request_stats.runnable++; __i915_request_submit(request); intel_engine_init_global_seqno(request->engine, request->global_seqno); spin_unlock_irqrestore(&request->engine->timeline.lock, flags); diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index abd4dacbab8e..689f838e849c 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -457,6 +457,9 @@ void __i915_request_submit(struct i915_request *request) /* Transfer from per-context onto the global per-engine timeline */ move_to_timeline(request, &engine->timeline); + GEM_BUG_ON(engine->request_stats.runnable == 0); + engine->request_stats.runnable--; + trace_i915_request_execute(request); wake_up_all(&request->execute); @@ -470,6 +473,8 @@ void i915_request_submit(struct i915_request *request) /* Will be called from irq-context when using foreign fences. */ spin_lock_irqsave(&engine->timeline.lock, flags); + engine->request_stats.runnable++; + __i915_request_submit(request); spin_unlock_irqrestore(&engine->timeline.lock, flags); @@ -507,6 +512,8 @@ void __i915_request_unsubmit(struct i915_request *request) /* Transfer back from the global per-engine timeline to per-context */ move_to_timeline(request, request->timeline); + engine->request_stats.runnable++; + /* * We don't need to wake_up any waiters on request->execute, they * will get woken by any other event or us re-adding this request diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 1c6143bdf5a4..f46ef765aed0 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1460,11 +1460,12 @@ void intel_engine_dump(struct intel_engine_cs *engine, if (i915_terminally_wedged(&engine->i915->gpu_error)) drm_printf(m, "*** WEDGED ***\n"); - drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms]\n", + drm_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms], runnable %u\n", intel_engine_get_seqno(engine), intel_engine_last_submit(engine), engine->hangcheck.seqno, - jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp)); + jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp), + engine->request_stats.runnable); drm_printf(m, "\tReset count: %d (global %d)\n", i915_reset_engine_count(error, engine), i915_reset_count(error)); diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 28d56387edf5..f0c2673fce49 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1023,6 +1023,7 @@ static void queue_request(struct intel_engine_cs *engine, int prio) { list_add_tail(&node->link, i915_sched_lookup_priolist(engine, prio)); + engine->request_stats.runnable++; } static void __submit_queue_imm(struct intel_engine_cs *engine) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 7078132fc631..07491b6c7796 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -380,6 +380,15 @@ struct intel_engine_cs { struct drm_i915_gem_object *default_state; void *pinned_default_state; + struct { + /** + * @runnable: Number of runnable requests sent to the backend. + * + * Count of requests waiting for the GPU to execute them. + */ + unsigned int runnable; + } request_stats; + unsigned long irq_posted; #define ENGINE_IRQ_BREADCRUMB 0