From patchwork Wed Oct 3 12:03:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10624715 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A78BA14BD for ; Wed, 3 Oct 2018 12:04:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9B0AE28944 for ; Wed, 3 Oct 2018 12:04:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8F5D028957; Wed, 3 Oct 2018 12:04:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 25DF728944 for ; Wed, 3 Oct 2018 12:04:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 481E56E460; Wed, 3 Oct 2018 12:04:35 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by gabe.freedesktop.org (Postfix) with ESMTPS id 060DA6E454 for ; Wed, 3 Oct 2018 12:04:19 +0000 (UTC) Received: by mail-wm1-x332.google.com with SMTP id s12-v6so5464063wmc.0 for ; Wed, 03 Oct 2018 05:04:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RUbuRUHFq1oXnphC7jdtaCFdSwpWxe7psGDajscRPvA=; b=eHZhjhfut64pwoemFS2yMsyMA2klMBPr/hfhhYfD5jAntS7U7r4/9BsVAL0S26Od+t Ek6WQbpike68TdkCnLpG3WwYyaFxUyjdLMO7LENoP9TmOnGbNwCa23+syzrr+ChPYxx9 MQQ+4fWI6YuiMa3cq5c0SJd9oNh1JCWN2r4KHN+KgeATKeweIBH03kAWgW0Ggj4WP9dJ iDhnN3abUGKE5O78POVtW1Zsyi6ONpgDILBu4ob0Y32ufl93oQpgjUJw49Ni9MMZ2MW7 D6643dp/FaTVkGBT5/X3rNNrhglG8yRG1p1+j59u6MwLrdU1QpClLrIfQPaRELcPecK4 pLGQ== X-Gm-Message-State: ABuFfojw8lbI0hW6tbLCk0LhJ1xdbFXSr+x7M7uXi4jz2+I8dE0n6H86 GwE1ytjtvDUhHyQWgJcSN6JUkcFS31g= X-Google-Smtp-Source: ACcGV60PP+8lK0CGhwV+e8uSDvkA7QkkUZe72KTR5c+rYd/cOVAiiftN9i+qQgnptAavj0OIwK3nOw== X-Received: by 2002:a1c:1fc2:: with SMTP id f185-v6mr1203152wmf.18.1538568257313; Wed, 03 Oct 2018 05:04:17 -0700 (PDT) Received: from localhost.localdomain ([95.144.165.37]) by smtp.gmail.com with ESMTPSA id f69-v6sm866657wmf.34.2018.10.03.05.04.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Oct 2018 05:04:16 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Wed, 3 Oct 2018 13:03:58 +0100 Message-Id: <20181003120406.6784-6-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181003120406.6784-1-tvrtko.ursulin@linux.intel.com> References: <20181003120406.6784-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [RFC 05/13] drm/i915/pmu: Add runnable counter X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin We add a PMU counter to expose the number of requests with resolved dependencies waiting for a slot on the GPU to run. This is useful to analyze the overall load of the system. v2: Don't limit to gen8+. v3: * Rebase for dynamic sysfs. * Drop currently executing requests. v4: * Sync with internal renaming. * Drop floating point constant. (Chris Wilson) v5: * Change scale to 1024 for faster arithmetics. (Chris Wilson) v6: * Refactored for timer period accounting. v7: * Avoid 64-division. (Chris Wilson) v8: * Do fewer divisions by accumulating in qd.ns units. (Chris Wilson) * Change counter scale to avoid multiplication in readout and increase counter headroom. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_pmu.c | 20 ++++++++++++++++++-- drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +- include/uapi/drm/i915_drm.h | 7 ++++++- 3 files changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 13449537e2a7..b01a2e66d33a 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -17,7 +17,8 @@ (BIT(I915_SAMPLE_BUSY) | \ BIT(I915_SAMPLE_WAIT) | \ BIT(I915_SAMPLE_SEMA) | \ - BIT(I915_SAMPLE_QUEUED)) + BIT(I915_SAMPLE_QUEUED) | \ + BIT(I915_SAMPLE_RUNNABLE)) #define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS) @@ -217,6 +218,11 @@ engines_sample(struct drm_i915_private *dev_priv, unsigned int period_ns) add_sample_mult(&engine->pmu.sample[I915_SAMPLE_QUEUED], atomic_read(&engine->request_stats.queued), period_ns); + + if (engine->pmu.enable & BIT(I915_SAMPLE_RUNNABLE)) + add_sample_mult(&engine->pmu.sample[I915_SAMPLE_RUNNABLE], + engine->request_stats.runnable, + period_ns); } if (fw) @@ -331,6 +337,7 @@ engine_event_status(struct intel_engine_cs *engine, case I915_SAMPLE_BUSY: case I915_SAMPLE_WAIT: case I915_SAMPLE_QUEUED: + case I915_SAMPLE_RUNNABLE: break; case I915_SAMPLE_SEMA: if (INTEL_GEN(engine->i915) < 6) @@ -549,9 +556,12 @@ static u64 __i915_pmu_event_read(struct perf_event *event) } else { val = engine->pmu.sample[sample].cur; - if (sample == I915_SAMPLE_QUEUED) { + if (sample == I915_SAMPLE_QUEUED || + sample == I915_SAMPLE_RUNNABLE) { BUILD_BUG_ON(NSEC_PER_SEC % I915_SAMPLE_QUEUED_DIVISOR); + BUILD_BUG_ON(I915_SAMPLE_QUEUED_DIVISOR != + I915_SAMPLE_RUNNABLE_DIVISOR); /* to qd */ val = div_u64(val, NSEC_PER_SEC / @@ -852,6 +862,7 @@ add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name, /* No brackets or quotes below please. */ #define I915_SAMPLE_QUEUED_SCALE 0.001 +#define I915_SAMPLE_RUNNABLE_SCALE 0.001 static struct attribute ** create_event_attributes(struct drm_i915_private *i915) @@ -877,6 +888,8 @@ create_event_attributes(struct drm_i915_private *i915) __engine_event(I915_SAMPLE_WAIT, "wait"), __engine_event_scale(I915_SAMPLE_QUEUED, "queued", __stringify(I915_SAMPLE_QUEUED_SCALE)), + __engine_event_scale(I915_SAMPLE_RUNNABLE, "runnable", + __stringify(I915_SAMPLE_RUNNABLE_SCALE)), }; unsigned int count = 0; struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter; @@ -889,6 +902,9 @@ create_event_attributes(struct drm_i915_private *i915) BUILD_BUG_ON(I915_SAMPLE_QUEUED_DIVISOR != (1 / I915_SAMPLE_QUEUED_SCALE)); + BUILD_BUG_ON(I915_SAMPLE_RUNNABLE_DIVISOR != + (1 / I915_SAMPLE_RUNNABLE_SCALE)); + /* Count how many counters we will be exposing. */ for (i = 0; i < ARRAY_SIZE(events); i++) { if (!config_status(i915, events[i].config)) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index b44dee354dc6..50914b0ed826 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -455,7 +455,7 @@ struct intel_engine_cs { * * Our internal timer stores the current counters in this field. */ -#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_QUEUED + 1) +#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_RUNNABLE + 1) struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX]; } pmu; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index dc76c4102c7a..5bb7f53f1a3d 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -111,11 +111,13 @@ enum drm_i915_pmu_engine_sample { I915_SAMPLE_BUSY = 0, I915_SAMPLE_WAIT = 1, I915_SAMPLE_SEMA = 2, - I915_SAMPLE_QUEUED = 3 + I915_SAMPLE_QUEUED = 3, + I915_SAMPLE_RUNNABLE = 4, }; /* Divide counter value by divisor to get the real value. */ #define I915_SAMPLE_QUEUED_DIVISOR (1000) +#define I915_SAMPLE_RUNNABLE_DIVISOR (1000) #define I915_PMU_SAMPLE_BITS (4) #define I915_PMU_SAMPLE_MASK (0xf) @@ -140,6 +142,9 @@ enum drm_i915_pmu_engine_sample { #define I915_PMU_ENGINE_QUEUED(class, instance) \ __I915_PMU_ENGINE(class, instance, I915_SAMPLE_QUEUED) +#define I915_PMU_ENGINE_RUNNABLE(class, instance) \ + __I915_PMU_ENGINE(class, instance, I915_SAMPLE_RUNNABLE) + #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)