| Message ID | 20181005232306.31133-21-manasi.d.navare@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Display Stream Compression enabling on eDP/DP | expand |
>-----Original Message----- >From: Navare, Manasi D >Sent: Friday, October 5, 2018 4:23 PM >To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org >Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Jani Nikula ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; >Srivatsa, Anusha <anusha.srivatsa@intel.com> >Subject: [PATCH v5 20/28] drm/i915/dp: Configure i915 Picture parameter Set >registers during DSC enabling > >After encoder->pre_enable() hook, after link training sequence is completed, PPS >registers for DSC encoder are configured using the DSC state parameters in >intel_crtc_state as part of DSC enabling routine in the source. DSC enabling >routine is called after >encoder->pre_enable() before enbaling the pipe and after >compression is enabled on the sink. > >v3: >* Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe >are used (Manasi) >* Add DSC slice_row_per_frame in PPS16 (Manasi) > >v2: >* Enable PG2 power well for VDSC on eDP > >Cc: Jani Nikula <jani.nikula@linux.intel.com> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> >--- > drivers/gpu/drm/i915/i915_drv.h | 2 + > drivers/gpu/drm/i915/intel_display.c | 6 + > drivers/gpu/drm/i915/intel_vdsc.c | 418 +++++++++++++++++++++++++++ > 3 files changed, 426 insertions(+) > >diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >index 93e57b271d3b..b49985f5d08c 100644 >--- a/drivers/gpu/drm/i915/i915_drv.h >+++ b/drivers/gpu/drm/i915/i915_drv.h >@@ -3506,6 +3506,8 @@ extern void intel_rps_mark_interactive(struct >drm_i915_private *i915, > bool interactive); > extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, > bool enable); >+extern void intel_dsc_enable(struct intel_encoder *encoder, >+ struct intel_crtc_state *crtc_state); > > int i915_reg_read_ioctl(struct drm_device *dev, void *data, > struct drm_file *file); >diff --git a/drivers/gpu/drm/i915/intel_display.c >b/drivers/gpu/drm/i915/intel_display.c >index 4ebf7c83085c..f7cb41775c57 100644 >--- a/drivers/gpu/drm/i915/intel_display.c >+++ b/drivers/gpu/drm/i915/intel_display.c >@@ -5480,6 +5480,12 @@ static void intel_encoders_pre_enable(struct >drm_crtc *crtc, > > if (encoder->pre_enable) > encoder->pre_enable(encoder, crtc_state, conn_state); >+ >+ /* >+ * Enable and Configure Display Stream Compression in the >source >+ * if enabled in intel_crtc_state. >+ */ >+ intel_dsc_enable(encoder, crtc_state); > } > } > >diff --git a/drivers/gpu/drm/i915/intel_vdsc.c >b/drivers/gpu/drm/i915/intel_vdsc.c >index 594196a9d0f4..1f2b5dc82f16 100644 >--- a/drivers/gpu/drm/i915/intel_vdsc.c >+++ b/drivers/gpu/drm/i915/intel_vdsc.c >@@ -580,3 +580,421 @@ int intel_dp_compute_dsc_params(struct intel_dp >*intel_dp, > > return 0; > } >+ >+static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, >+ struct intel_crtc_state >*crtc_state) { >+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); >+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >+ struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; >+ enum pipe pipe = crtc->pipe; >+ u32 pps_val = 0; >+ u32 rc_buf_thresh_dword[4]; >+ u32 rc_range_params_dword[8]; >+ u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1; >+ int i = 0; >+ >+ /* Populate PICTURE_PARAMETER_SET_0 registers */ >+ pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << >+ DSC_VER_MIN_SHIFT | >+ vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | >+ vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; >+ if (vdsc_cfg->block_pred_enable) >+ pps_val |= DSC_BLOCK_PREDICTION; >+ else >+ pps_val &= ~DSC_BLOCK_PREDICTION; >+ if (vdsc_cfg->convert_rgb) >+ pps_val |= DSC_COLOR_SPACE_CONVERSION; >+ else >+ pps_val &= ~DSC_COLOR_SPACE_CONVERSION; >+ if (vdsc_cfg->enable422) >+ pps_val |= DSC_422_ENABLE; >+ else >+ pps_val &= ~DSC_422_ENABLE; >+ if (vdsc_cfg->vbr_enable) >+ pps_val |= DSC_VBR_ENABLE; >+ else >+ pps_val &= ~DSC_VBR_ENABLE; >+ >+ DRM_INFO("PPS0 = 0x%08x\n", pps_val); >+ if (encoder->type == INTEL_OUTPUT_EDP) { >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val); >+ /* >+ * If 2 VDSC instances are needed, configure PPS for second >+ * VDSC >+ */ >+ if (crtc_state->dsc_params.dsc_split) >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, >pps_val); >+ } else { >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), >pps_val); >+ if (crtc_state->dsc_params.dsc_split) >+ > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), >+ pps_val); >+ } >+ >+ /* Populate PICTURE_PARAMETER_SET_1 registers */ >+ pps_val = 0; >+ pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); >+ DRM_INFO("PPS1 = 0x%08x\n", pps_val); >+ if (encoder->type == INTEL_OUTPUT_EDP) { >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val); >+ /* >+ * If 2 VDSC instances are needed, configure PPS for second >+ * VDSC >+ */ >+ if (crtc_state->dsc_params.dsc_split) >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, >pps_val); >+ } else { >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), >pps_val); >+ if (crtc_state->dsc_params.dsc_split) >+ > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), >+ pps_val); >+ } >+ >+ /* Populate PICTURE_PARAMETER_SET_2 registers */ >+ pps_val = 0; >+ pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | >+ DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); >+ DRM_INFO("PPS2 = 0x%08x\n", pps_val); >+ if (encoder->type == INTEL_OUTPUT_EDP) { >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); >+ /* >+ * If 2 VDSC instances are needed, configure PPS for second >+ * VDSC >+ */ >+ if (crtc_state->dsc_params.dsc_split) >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, >pps_val); >+ } else { >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), >pps_val); >+ if (crtc_state->dsc_params.dsc_split) >+ > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), >+ pps_val); >+ } >+ >+ /* Populate PICTURE_PARAMETER_SET_3 registers */ >+ pps_val = 0; >+ pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | >+ DSC_SLICE_WIDTH(vdsc_cfg->slice_width); >+ DRM_INFO("PPS3 = 0x%08x\n", pps_val); >+ if (encoder->type == INTEL_OUTPUT_EDP) { >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val); >+ /* >+ * If 2 VDSC instances are needed, configure PPS for second >+ * VDSC >+ */ >+ if (crtc_state->dsc_params.dsc_split) >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, >pps_val); >+ } else { >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), >pps_val); >+ if (crtc_state->dsc_params.dsc_split) >+ > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), >+ pps_val); >+ } >+ >+ /* Populate PICTURE_PARAMETER_SET_4 registers */ >+ pps_val = 0; >+ pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | >+ DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); >+ DRM_INFO("PPS4 = 0x%08x\n", pps_val); >+ if (encoder->type == INTEL_OUTPUT_EDP) { >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val); >+ /* >+ * If 2 VDSC instances are needed, configure PPS for second >+ * VDSC >+ */ >+ if (crtc_state->dsc_params.dsc_split) >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, >pps_val); >+ } else { >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), >pps_val); >+ if (crtc_state->dsc_params.dsc_split) >+ > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), >+ pps_val); >+ } >+ >+ /* Populate PICTURE_PARAMETER_SET_5 registers */ >+ pps_val = 0; >+ pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | >+ DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); >+ DRM_INFO("PPS5 = 0x%08x\n", pps_val); >+ if (encoder->type == INTEL_OUTPUT_EDP) { >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val); >+ /* >+ * If 2 VDSC instances are needed, configure PPS for second >+ * VDSC >+ */ >+ if (crtc_state->dsc_params.dsc_split) >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, >pps_val); >+ } else { >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), >pps_val); >+ if (crtc_state->dsc_params.dsc_split) >+ > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), >+ pps_val); >+ } >+ >+ /* Populate PICTURE_PARAMETER_SET_6 registers */ >+ pps_val = 0; >+ pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | >+ DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) >| >+ DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | >+ DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); >+ DRM_INFO("PPS6 = 0x%08x\n", pps_val); >+ if (encoder->type == INTEL_OUTPUT_EDP) { >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val); >+ /* >+ * If 2 VDSC instances are needed, configure PPS for second >+ * VDSC >+ */ >+ if (crtc_state->dsc_params.dsc_split) >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, >pps_val); >+ } else { >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), >pps_val); >+ if (crtc_state->dsc_params.dsc_split) >+ > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), >+ pps_val); >+ } >+ >+ /* Populate PICTURE_PARAMETER_SET_7 registers */ >+ pps_val = 0; >+ pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | >+ DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); >+ DRM_INFO("PPS7 = 0x%08x\n", pps_val); >+ if (encoder->type == INTEL_OUTPUT_EDP) { >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val); >+ /* >+ * If 2 VDSC instances are needed, configure PPS for second >+ * VDSC >+ */ >+ if (crtc_state->dsc_params.dsc_split) >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, >pps_val); >+ } else { >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), >pps_val); >+ if (crtc_state->dsc_params.dsc_split) >+ > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), >+ pps_val); >+ } >+ >+ /* Populate PICTURE_PARAMETER_SET_8 registers */ >+ pps_val = 0; >+ pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | >+ DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); >+ DRM_INFO("PPS8 = 0x%08x\n", pps_val); >+ if (encoder->type == INTEL_OUTPUT_EDP) { >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val); >+ /* >+ * If 2 VDSC instances are needed, configure PPS for second >+ * VDSC >+ */ >+ if (crtc_state->dsc_params.dsc_split) >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, >pps_val); >+ } else { >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), >pps_val); >+ if (crtc_state->dsc_params.dsc_split) >+ > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), >+ pps_val); >+ } >+ >+ /* Populate PICTURE_PARAMETER_SET_9 registers */ >+ pps_val = 0; >+ pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) | >+ DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); >+ DRM_INFO("PPS9 = 0x%08x\n", pps_val); >+ if (encoder->type == INTEL_OUTPUT_EDP) { >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val); >+ /* >+ * If 2 VDSC instances are needed, configure PPS for second >+ * VDSC >+ */ >+ if (crtc_state->dsc_params.dsc_split) >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, >pps_val); >+ } else { >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), >pps_val); >+ if (crtc_state->dsc_params.dsc_split) >+ > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), >+ pps_val); >+ } >+ >+ /* Populate PICTURE_PARAMETER_SET_10 registers */ >+ pps_val = 0; >+ pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg- >>rc_quant_incr_limit0) | >+ DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | >+ DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | >+ DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); >+ DRM_INFO("PPS10 = 0x%08x\n", pps_val); >+ if (encoder->type == INTEL_OUTPUT_EDP) { >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val); >+ /* >+ * If 2 VDSC instances are needed, configure PPS for second >+ * VDSC >+ */ >+ if (crtc_state->dsc_params.dsc_split) >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, >pps_val); >+ } else { >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), >pps_val); >+ if (crtc_state->dsc_params.dsc_split) >+ > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), >+ pps_val); >+ } >+ >+ /* Populate the RC_BUF_THRESH registers */ >+ memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); >+ for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { >+ rc_buf_thresh_dword[i/4] |= (u32)(vdsc_cfg->rc_buf_thresh[i] << >+ BITS_PER_BYTE * (i % 4)); >+ DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i, >+ rc_buf_thresh_dword[i/4]); >+ } >+ if (encoder->type == INTEL_OUTPUT_EDP) { >+ I915_WRITE(DSCA_RC_BUF_THRESH_0, >rc_buf_thresh_dword[0]); >+ I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, >rc_buf_thresh_dword[1]); >+ I915_WRITE(DSCA_RC_BUF_THRESH_1, >rc_buf_thresh_dword[2]); >+ I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, >rc_buf_thresh_dword[3]); >+ if (crtc_state->dsc_params.dsc_split) { >+ I915_WRITE(DSCC_RC_BUF_THRESH_0, >+ rc_buf_thresh_dword[0]); >+ I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW, >+ rc_buf_thresh_dword[1]); >+ I915_WRITE(DSCC_RC_BUF_THRESH_1, >+ rc_buf_thresh_dword[2]); >+ I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW, >+ rc_buf_thresh_dword[3]); >+ } >+ } else { >+ I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe), >+ rc_buf_thresh_dword[0]); >+ I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), >+ rc_buf_thresh_dword[1]); >+ I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe), >+ rc_buf_thresh_dword[2]); >+ I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), >+ rc_buf_thresh_dword[3]); >+ if (crtc_state->dsc_params.dsc_split) { >+ I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe), >+ rc_buf_thresh_dword[0]); >+ I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), >+ rc_buf_thresh_dword[1]); >+ I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe), >+ rc_buf_thresh_dword[2]); >+ I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), >+ rc_buf_thresh_dword[3]); >+ } >+ } >+ >+ /* Populate the RC_RANGE_PARAMETERS registers */ >+ memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); >+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { >+ rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg- >>rc_range_params[i].range_bpg_offset << >+ RC_BPG_OFFSET_SHIFT) | >+ (vdsc_cfg- >>rc_range_params[i].range_max_qp << >+ RC_MAX_QP_SHIFT) | >+ (vdsc_cfg- >>rc_range_params[i].range_min_qp << >+ RC_MIN_QP_SHIFT)) << 16 * >(i % 2)); >+ DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i, >+ rc_range_params_dword[i/2]); >+ } >+ if (encoder->type == INTEL_OUTPUT_EDP) { >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0, >+ rc_range_params_dword[0]); >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW, >+ rc_range_params_dword[1]); >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1, >+ rc_range_params_dword[2]); >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW, >+ rc_range_params_dword[3]); >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2, >+ rc_range_params_dword[4]); >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW, >+ rc_range_params_dword[5]); >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3, >+ rc_range_params_dword[6]); >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW, >+ rc_range_params_dword[7]); >+ if (crtc_state->dsc_params.dsc_split) { >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0, >+ rc_range_params_dword[0]); >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW, >+ rc_range_params_dword[1]); >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1, >+ rc_range_params_dword[2]); >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW, >+ rc_range_params_dword[3]); >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2, >+ rc_range_params_dword[4]); >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW, >+ rc_range_params_dword[5]); >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3, >+ rc_range_params_dword[6]); >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW, >+ rc_range_params_dword[7]); >+ } >+ } else { >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), >+ rc_range_params_dword[0]); >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), >+ rc_range_params_dword[1]); >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), >+ rc_range_params_dword[2]); >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), >+ rc_range_params_dword[3]); >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), >+ rc_range_params_dword[4]); >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), >+ rc_range_params_dword[5]); >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), >+ rc_range_params_dword[6]); >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), >+ rc_range_params_dword[7]); >+ if (crtc_state->dsc_params.dsc_split) { >+ > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), >+ rc_range_params_dword[0]); >+ > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), >+ rc_range_params_dword[1]); >+ > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), >+ rc_range_params_dword[2]); >+ > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), >+ rc_range_params_dword[3]); >+ > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), >+ rc_range_params_dword[4]); >+ > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), >+ rc_range_params_dword[5]); >+ > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), >+ rc_range_params_dword[6]); >+ > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), >+ rc_range_params_dword[7]); >+ } >+ } Any specific reason for PPS16 to be after RC_RANGE_PARAMETERS and RC_BUF_THRESH? Anusha >+ /* Populate Picture parameter set 16 */ >+ pps_val = 0; >+ pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | >+ DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / >num_vdsc_instances) / >+ vdsc_cfg->slice_width) | >+ DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / >+ vdsc_cfg->slice_height); >+ DRM_INFO("PPS16 = 0x%08x\n", pps_val); >+ if (encoder->type == INTEL_OUTPUT_EDP) { >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val); >+ /* >+ * If 2 VDSC instances are needed, configure PPS for second >+ * VDSC >+ */ >+ if (crtc_state->dsc_params.dsc_split) >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, >pps_val); >+ } else { >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), >pps_val); >+ if (crtc_state->dsc_params.dsc_split) >+ > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), >+ pps_val); >+ } >+} >+ >+void intel_dsc_enable(struct intel_encoder *encoder, >+ struct intel_crtc_state *crtc_state) { >+ >+ if (!crtc_state->dsc_params.compression_enable) >+ return; >+ >+ intel_configure_pps_for_dsc_encoder(encoder, crtc_state); >+ >+ return; >+} >-- >2.18.0
On Tue, Oct 16, 2018 at 12:58:24PM -0700, Srivatsa, Anusha wrote: > > > >-----Original Message----- > >From: Navare, Manasi D > >Sent: Friday, October 5, 2018 4:23 PM > >To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org > >Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Jani Nikula > ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; > >Srivatsa, Anusha <anusha.srivatsa@intel.com> > >Subject: [PATCH v5 20/28] drm/i915/dp: Configure i915 Picture parameter Set > >registers during DSC enabling > > > >After encoder->pre_enable() hook, after link training sequence is completed, PPS > >registers for DSC encoder are configured using the DSC state parameters in > >intel_crtc_state as part of DSC enabling routine in the source. DSC enabling > >routine is called after > >encoder->pre_enable() before enbaling the pipe and after > >compression is enabled on the sink. > > > >v3: > >* Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe > >are used (Manasi) > >* Add DSC slice_row_per_frame in PPS16 (Manasi) > > > >v2: > >* Enable PG2 power well for VDSC on eDP > > > >Cc: Jani Nikula <jani.nikula@linux.intel.com> > >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> > >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > > >--- > > drivers/gpu/drm/i915/i915_drv.h | 2 + > > drivers/gpu/drm/i915/intel_display.c | 6 + > > drivers/gpu/drm/i915/intel_vdsc.c | 418 +++++++++++++++++++++++++++ > > 3 files changed, 426 insertions(+) > > > >diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > >index 93e57b271d3b..b49985f5d08c 100644 > >--- a/drivers/gpu/drm/i915/i915_drv.h > >+++ b/drivers/gpu/drm/i915/i915_drv.h > >@@ -3506,6 +3506,8 @@ extern void intel_rps_mark_interactive(struct > >drm_i915_private *i915, > > bool interactive); > > extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, > > bool enable); > >+extern void intel_dsc_enable(struct intel_encoder *encoder, > >+ struct intel_crtc_state *crtc_state); > > > > int i915_reg_read_ioctl(struct drm_device *dev, void *data, > > struct drm_file *file); > >diff --git a/drivers/gpu/drm/i915/intel_display.c > >b/drivers/gpu/drm/i915/intel_display.c > >index 4ebf7c83085c..f7cb41775c57 100644 > >--- a/drivers/gpu/drm/i915/intel_display.c > >+++ b/drivers/gpu/drm/i915/intel_display.c > >@@ -5480,6 +5480,12 @@ static void intel_encoders_pre_enable(struct > >drm_crtc *crtc, > > > > if (encoder->pre_enable) > > encoder->pre_enable(encoder, crtc_state, conn_state); > >+ > >+ /* > >+ * Enable and Configure Display Stream Compression in the > >source > >+ * if enabled in intel_crtc_state. > >+ */ > >+ intel_dsc_enable(encoder, crtc_state); > > } > > } > > > >diff --git a/drivers/gpu/drm/i915/intel_vdsc.c > >b/drivers/gpu/drm/i915/intel_vdsc.c > >index 594196a9d0f4..1f2b5dc82f16 100644 > >--- a/drivers/gpu/drm/i915/intel_vdsc.c > >+++ b/drivers/gpu/drm/i915/intel_vdsc.c > >@@ -580,3 +580,421 @@ int intel_dp_compute_dsc_params(struct intel_dp > >*intel_dp, > > > > return 0; > > } > >+ > >+static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, > >+ struct intel_crtc_state > >*crtc_state) { > >+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > >+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >+ struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; > >+ enum pipe pipe = crtc->pipe; > >+ u32 pps_val = 0; > >+ u32 rc_buf_thresh_dword[4]; > >+ u32 rc_range_params_dword[8]; > >+ u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1; > >+ int i = 0; > >+ > >+ /* Populate PICTURE_PARAMETER_SET_0 registers */ > >+ pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << > >+ DSC_VER_MIN_SHIFT | > >+ vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | > >+ vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; > >+ if (vdsc_cfg->block_pred_enable) > >+ pps_val |= DSC_BLOCK_PREDICTION; > >+ else > >+ pps_val &= ~DSC_BLOCK_PREDICTION; > >+ if (vdsc_cfg->convert_rgb) > >+ pps_val |= DSC_COLOR_SPACE_CONVERSION; > >+ else > >+ pps_val &= ~DSC_COLOR_SPACE_CONVERSION; > >+ if (vdsc_cfg->enable422) > >+ pps_val |= DSC_422_ENABLE; > >+ else > >+ pps_val &= ~DSC_422_ENABLE; > >+ if (vdsc_cfg->vbr_enable) > >+ pps_val |= DSC_VBR_ENABLE; > >+ else > >+ pps_val &= ~DSC_VBR_ENABLE; > >+ > >+ DRM_INFO("PPS0 = 0x%08x\n", pps_val); > >+ if (encoder->type == INTEL_OUTPUT_EDP) { > >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val); > >+ /* > >+ * If 2 VDSC instances are needed, configure PPS for second > >+ * VDSC > >+ */ > >+ if (crtc_state->dsc_params.dsc_split) > >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, > >pps_val); > >+ } else { > >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), > >pps_val); > >+ if (crtc_state->dsc_params.dsc_split) > >+ > > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), > >+ pps_val); > >+ } > >+ > >+ /* Populate PICTURE_PARAMETER_SET_1 registers */ > >+ pps_val = 0; > >+ pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); > >+ DRM_INFO("PPS1 = 0x%08x\n", pps_val); > >+ if (encoder->type == INTEL_OUTPUT_EDP) { > >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val); > >+ /* > >+ * If 2 VDSC instances are needed, configure PPS for second > >+ * VDSC > >+ */ > >+ if (crtc_state->dsc_params.dsc_split) > >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, > >pps_val); > >+ } else { > >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), > >pps_val); > >+ if (crtc_state->dsc_params.dsc_split) > >+ > > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), > >+ pps_val); > >+ } > >+ > >+ /* Populate PICTURE_PARAMETER_SET_2 registers */ > >+ pps_val = 0; > >+ pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | > >+ DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); > >+ DRM_INFO("PPS2 = 0x%08x\n", pps_val); > >+ if (encoder->type == INTEL_OUTPUT_EDP) { > >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); > >+ /* > >+ * If 2 VDSC instances are needed, configure PPS for second > >+ * VDSC > >+ */ > >+ if (crtc_state->dsc_params.dsc_split) > >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, > >pps_val); > >+ } else { > >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), > >pps_val); > >+ if (crtc_state->dsc_params.dsc_split) > >+ > > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), > >+ pps_val); > >+ } > >+ > >+ /* Populate PICTURE_PARAMETER_SET_3 registers */ > >+ pps_val = 0; > >+ pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | > >+ DSC_SLICE_WIDTH(vdsc_cfg->slice_width); > >+ DRM_INFO("PPS3 = 0x%08x\n", pps_val); > >+ if (encoder->type == INTEL_OUTPUT_EDP) { > >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val); > >+ /* > >+ * If 2 VDSC instances are needed, configure PPS for second > >+ * VDSC > >+ */ > >+ if (crtc_state->dsc_params.dsc_split) > >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, > >pps_val); > >+ } else { > >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), > >pps_val); > >+ if (crtc_state->dsc_params.dsc_split) > >+ > > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), > >+ pps_val); > >+ } > >+ > >+ /* Populate PICTURE_PARAMETER_SET_4 registers */ > >+ pps_val = 0; > >+ pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | > >+ DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); > >+ DRM_INFO("PPS4 = 0x%08x\n", pps_val); > >+ if (encoder->type == INTEL_OUTPUT_EDP) { > >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val); > >+ /* > >+ * If 2 VDSC instances are needed, configure PPS for second > >+ * VDSC > >+ */ > >+ if (crtc_state->dsc_params.dsc_split) > >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, > >pps_val); > >+ } else { > >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), > >pps_val); > >+ if (crtc_state->dsc_params.dsc_split) > >+ > > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), > >+ pps_val); > >+ } > >+ > >+ /* Populate PICTURE_PARAMETER_SET_5 registers */ > >+ pps_val = 0; > >+ pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | > >+ DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); > >+ DRM_INFO("PPS5 = 0x%08x\n", pps_val); > >+ if (encoder->type == INTEL_OUTPUT_EDP) { > >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val); > >+ /* > >+ * If 2 VDSC instances are needed, configure PPS for second > >+ * VDSC > >+ */ > >+ if (crtc_state->dsc_params.dsc_split) > >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, > >pps_val); > >+ } else { > >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), > >pps_val); > >+ if (crtc_state->dsc_params.dsc_split) > >+ > > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), > >+ pps_val); > >+ } > >+ > >+ /* Populate PICTURE_PARAMETER_SET_6 registers */ > >+ pps_val = 0; > >+ pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | > >+ DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) > >| > >+ DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | > >+ DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); > >+ DRM_INFO("PPS6 = 0x%08x\n", pps_val); > >+ if (encoder->type == INTEL_OUTPUT_EDP) { > >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val); > >+ /* > >+ * If 2 VDSC instances are needed, configure PPS for second > >+ * VDSC > >+ */ > >+ if (crtc_state->dsc_params.dsc_split) > >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, > >pps_val); > >+ } else { > >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), > >pps_val); > >+ if (crtc_state->dsc_params.dsc_split) > >+ > > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), > >+ pps_val); > >+ } > >+ > >+ /* Populate PICTURE_PARAMETER_SET_7 registers */ > >+ pps_val = 0; > >+ pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | > >+ DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); > >+ DRM_INFO("PPS7 = 0x%08x\n", pps_val); > >+ if (encoder->type == INTEL_OUTPUT_EDP) { > >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val); > >+ /* > >+ * If 2 VDSC instances are needed, configure PPS for second > >+ * VDSC > >+ */ > >+ if (crtc_state->dsc_params.dsc_split) > >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, > >pps_val); > >+ } else { > >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), > >pps_val); > >+ if (crtc_state->dsc_params.dsc_split) > >+ > > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), > >+ pps_val); > >+ } > >+ > >+ /* Populate PICTURE_PARAMETER_SET_8 registers */ > >+ pps_val = 0; > >+ pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | > >+ DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); > >+ DRM_INFO("PPS8 = 0x%08x\n", pps_val); > >+ if (encoder->type == INTEL_OUTPUT_EDP) { > >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val); > >+ /* > >+ * If 2 VDSC instances are needed, configure PPS for second > >+ * VDSC > >+ */ > >+ if (crtc_state->dsc_params.dsc_split) > >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, > >pps_val); > >+ } else { > >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), > >pps_val); > >+ if (crtc_state->dsc_params.dsc_split) > >+ > > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), > >+ pps_val); > >+ } > >+ > >+ /* Populate PICTURE_PARAMETER_SET_9 registers */ > >+ pps_val = 0; > >+ pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) | > >+ DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); > >+ DRM_INFO("PPS9 = 0x%08x\n", pps_val); > >+ if (encoder->type == INTEL_OUTPUT_EDP) { > >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val); > >+ /* > >+ * If 2 VDSC instances are needed, configure PPS for second > >+ * VDSC > >+ */ > >+ if (crtc_state->dsc_params.dsc_split) > >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, > >pps_val); > >+ } else { > >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), > >pps_val); > >+ if (crtc_state->dsc_params.dsc_split) > >+ > > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), > >+ pps_val); > >+ } > >+ > >+ /* Populate PICTURE_PARAMETER_SET_10 registers */ > >+ pps_val = 0; > >+ pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg- > >>rc_quant_incr_limit0) | > >+ DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | > >+ DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | > >+ DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); > >+ DRM_INFO("PPS10 = 0x%08x\n", pps_val); > >+ if (encoder->type == INTEL_OUTPUT_EDP) { > >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val); > >+ /* > >+ * If 2 VDSC instances are needed, configure PPS for second > >+ * VDSC > >+ */ > >+ if (crtc_state->dsc_params.dsc_split) > >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, > >pps_val); > >+ } else { > >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), > >pps_val); > >+ if (crtc_state->dsc_params.dsc_split) > >+ > > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), > >+ pps_val); > >+ } > >+ > >+ /* Populate the RC_BUF_THRESH registers */ > >+ memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); > >+ for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { > >+ rc_buf_thresh_dword[i/4] |= (u32)(vdsc_cfg->rc_buf_thresh[i] << > >+ BITS_PER_BYTE * (i % 4)); > >+ DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i, > >+ rc_buf_thresh_dword[i/4]); > >+ } > >+ if (encoder->type == INTEL_OUTPUT_EDP) { > >+ I915_WRITE(DSCA_RC_BUF_THRESH_0, > >rc_buf_thresh_dword[0]); > >+ I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, > >rc_buf_thresh_dword[1]); > >+ I915_WRITE(DSCA_RC_BUF_THRESH_1, > >rc_buf_thresh_dword[2]); > >+ I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, > >rc_buf_thresh_dword[3]); > >+ if (crtc_state->dsc_params.dsc_split) { > >+ I915_WRITE(DSCC_RC_BUF_THRESH_0, > >+ rc_buf_thresh_dword[0]); > >+ I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW, > >+ rc_buf_thresh_dword[1]); > >+ I915_WRITE(DSCC_RC_BUF_THRESH_1, > >+ rc_buf_thresh_dword[2]); > >+ I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW, > >+ rc_buf_thresh_dword[3]); > >+ } > >+ } else { > >+ I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe), > >+ rc_buf_thresh_dword[0]); > >+ I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), > >+ rc_buf_thresh_dword[1]); > >+ I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe), > >+ rc_buf_thresh_dword[2]); > >+ I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), > >+ rc_buf_thresh_dword[3]); > >+ if (crtc_state->dsc_params.dsc_split) { > >+ I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe), > >+ rc_buf_thresh_dword[0]); > >+ I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), > >+ rc_buf_thresh_dword[1]); > >+ I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe), > >+ rc_buf_thresh_dword[2]); > >+ I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), > >+ rc_buf_thresh_dword[3]); > >+ } > >+ } > >+ > >+ /* Populate the RC_RANGE_PARAMETERS registers */ > >+ memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); > >+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { > >+ rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg- > >>rc_range_params[i].range_bpg_offset << > >+ RC_BPG_OFFSET_SHIFT) | > >+ (vdsc_cfg- > >>rc_range_params[i].range_max_qp << > >+ RC_MAX_QP_SHIFT) | > >+ (vdsc_cfg- > >>rc_range_params[i].range_min_qp << > >+ RC_MIN_QP_SHIFT)) << 16 * > >(i % 2)); > >+ DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i, > >+ rc_range_params_dword[i/2]); > >+ } > >+ if (encoder->type == INTEL_OUTPUT_EDP) { > >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0, > >+ rc_range_params_dword[0]); > >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW, > >+ rc_range_params_dword[1]); > >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1, > >+ rc_range_params_dword[2]); > >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW, > >+ rc_range_params_dword[3]); > >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2, > >+ rc_range_params_dword[4]); > >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW, > >+ rc_range_params_dword[5]); > >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3, > >+ rc_range_params_dword[6]); > >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW, > >+ rc_range_params_dword[7]); > >+ if (crtc_state->dsc_params.dsc_split) { > >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0, > >+ rc_range_params_dword[0]); > >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW, > >+ rc_range_params_dword[1]); > >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1, > >+ rc_range_params_dword[2]); > >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW, > >+ rc_range_params_dword[3]); > >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2, > >+ rc_range_params_dword[4]); > >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW, > >+ rc_range_params_dword[5]); > >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3, > >+ rc_range_params_dword[6]); > >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW, > >+ rc_range_params_dword[7]); > >+ } > >+ } else { > >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), > >+ rc_range_params_dword[0]); > >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), > >+ rc_range_params_dword[1]); > >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), > >+ rc_range_params_dword[2]); > >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), > >+ rc_range_params_dword[3]); > >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), > >+ rc_range_params_dword[4]); > >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), > >+ rc_range_params_dword[5]); > >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), > >+ rc_range_params_dword[6]); > >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), > >+ rc_range_params_dword[7]); > >+ if (crtc_state->dsc_params.dsc_split) { > >+ > > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), > >+ rc_range_params_dword[0]); > >+ > > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), > >+ rc_range_params_dword[1]); > >+ > > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), > >+ rc_range_params_dword[2]); > >+ > > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), > >+ rc_range_params_dword[3]); > >+ > > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), > >+ rc_range_params_dword[4]); > >+ > > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), > >+ rc_range_params_dword[5]); > >+ > > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), > >+ rc_range_params_dword[6]); > >+ > > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), > >+ rc_range_params_dword[7]); > >+ } > >+ } > > Any specific reason for PPS16 to be after RC_RANGE_PARAMETERS and RC_BUF_THRESH? > > Anusha Thats just how its ordered in the bspec. Manasi > >+ /* Populate Picture parameter set 16 */ > >+ pps_val = 0; > >+ pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | > >+ DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / > >num_vdsc_instances) / > >+ vdsc_cfg->slice_width) | > >+ DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / > >+ vdsc_cfg->slice_height); > >+ DRM_INFO("PPS16 = 0x%08x\n", pps_val); > >+ if (encoder->type == INTEL_OUTPUT_EDP) { > >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val); > >+ /* > >+ * If 2 VDSC instances are needed, configure PPS for second > >+ * VDSC > >+ */ > >+ if (crtc_state->dsc_params.dsc_split) > >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, > >pps_val); > >+ } else { > >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), > >pps_val); > >+ if (crtc_state->dsc_params.dsc_split) > >+ > > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), > >+ pps_val); > >+ } > >+} > >+ > >+void intel_dsc_enable(struct intel_encoder *encoder, > >+ struct intel_crtc_state *crtc_state) { > >+ > >+ if (!crtc_state->dsc_params.compression_enable) > >+ return; > >+ > >+ intel_configure_pps_for_dsc_encoder(encoder, crtc_state); > >+ > >+ return; > >+} > >-- > >2.18.0 >
>-----Original Message----- >From: Navare, Manasi D >Sent: Tuesday, October 16, 2018 2:03 PM >To: Srivatsa, Anusha <anusha.srivatsa@intel.com> >Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Jani Nikula ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com> >Subject: Re: [PATCH v5 20/28] drm/i915/dp: Configure i915 Picture parameter Set >registers during DSC enabling > >On Tue, Oct 16, 2018 at 12:58:24PM -0700, Srivatsa, Anusha wrote: >> >> >> >-----Original Message----- >> >From: Navare, Manasi D >> >Sent: Friday, October 5, 2018 4:23 PM >> >To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org >> >Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Jani Nikula >> ><jani.nikula@linux.intel.com>; Ville Syrjala >> ><ville.syrjala@linux.intel.com>; Srivatsa, Anusha >> ><anusha.srivatsa@intel.com> >> >Subject: [PATCH v5 20/28] drm/i915/dp: Configure i915 Picture >> >parameter Set registers during DSC enabling >> > >> >After encoder->pre_enable() hook, after link training sequence is >> >completed, PPS registers for DSC encoder are configured using the DSC >> >state parameters in intel_crtc_state as part of DSC enabling routine >> >in the source. DSC enabling routine is called after >> >encoder->pre_enable() before enbaling the pipe and after >> >compression is enabled on the sink. >> > >> >v3: >> >* Configure Pic_width/2 for each VDSC engine when two VDSC engines >> >per pipe are used (Manasi) >> >* Add DSC slice_row_per_frame in PPS16 (Manasi) >> > >> >v2: >> >* Enable PG2 power well for VDSC on eDP >> > >> >Cc: Jani Nikula <jani.nikula@linux.intel.com> >> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Some comments inline..... >> >> >--- >> > drivers/gpu/drm/i915/i915_drv.h | 2 + >> > drivers/gpu/drm/i915/intel_display.c | 6 + >> > drivers/gpu/drm/i915/intel_vdsc.c | 418 +++++++++++++++++++++++++++ >> > 3 files changed, 426 insertions(+) >> > >> >diff --git a/drivers/gpu/drm/i915/i915_drv.h >> >b/drivers/gpu/drm/i915/i915_drv.h index 93e57b271d3b..b49985f5d08c >> >100644 >> >--- a/drivers/gpu/drm/i915/i915_drv.h >> >+++ b/drivers/gpu/drm/i915/i915_drv.h >> >@@ -3506,6 +3506,8 @@ extern void intel_rps_mark_interactive(struct >> >drm_i915_private *i915, >> > bool interactive); >> > extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, >> > bool enable); >> >+extern void intel_dsc_enable(struct intel_encoder *encoder, >> >+ struct intel_crtc_state *crtc_state); >> > >> > int i915_reg_read_ioctl(struct drm_device *dev, void *data, >> > struct drm_file *file); >> >diff --git a/drivers/gpu/drm/i915/intel_display.c >> >b/drivers/gpu/drm/i915/intel_display.c >> >index 4ebf7c83085c..f7cb41775c57 100644 >> >--- a/drivers/gpu/drm/i915/intel_display.c >> >+++ b/drivers/gpu/drm/i915/intel_display.c >> >@@ -5480,6 +5480,12 @@ static void intel_encoders_pre_enable(struct >> >drm_crtc *crtc, >> > >> > if (encoder->pre_enable) >> > encoder->pre_enable(encoder, crtc_state, conn_state); >> >+ >> >+ /* >> >+ * Enable and Configure Display Stream Compression in the >> >source >> >+ * if enabled in intel_crtc_state. >> >+ */ >> >+ intel_dsc_enable(encoder, crtc_state); >> > } >> > } >> > >> >diff --git a/drivers/gpu/drm/i915/intel_vdsc.c >> >b/drivers/gpu/drm/i915/intel_vdsc.c >> >index 594196a9d0f4..1f2b5dc82f16 100644 >> >--- a/drivers/gpu/drm/i915/intel_vdsc.c >> >+++ b/drivers/gpu/drm/i915/intel_vdsc.c >> >@@ -580,3 +580,421 @@ int intel_dp_compute_dsc_params(struct intel_dp >> >*intel_dp, >> > >> > return 0; >> > } >> >+ >> >+static void intel_configure_pps_for_dsc_encoder(struct intel_encoder >*encoder, >> >+ struct intel_crtc_state >> >*crtc_state) { >> >+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); >> >+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> >+ struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; >> >+ enum pipe pipe = crtc->pipe; >> >+ u32 pps_val = 0; >> >+ u32 rc_buf_thresh_dword[4]; >> >+ u32 rc_range_params_dword[8]; >> >+ u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1; >> >+ int i = 0; >> >+ >> >+ /* Populate PICTURE_PARAMETER_SET_0 registers */ >> >+ pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << >> >+ DSC_VER_MIN_SHIFT | >> >+ vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | >> >+ vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; >> >+ if (vdsc_cfg->block_pred_enable) >> >+ pps_val |= DSC_BLOCK_PREDICTION; >> >+ else >> >+ pps_val &= ~DSC_BLOCK_PREDICTION; >> >+ if (vdsc_cfg->convert_rgb) >> >+ pps_val |= DSC_COLOR_SPACE_CONVERSION; >> >+ else >> >+ pps_val &= ~DSC_COLOR_SPACE_CONVERSION; >> >+ if (vdsc_cfg->enable422) >> >+ pps_val |= DSC_422_ENABLE; >> >+ else >> >+ pps_val &= ~DSC_422_ENABLE; >> >+ if (vdsc_cfg->vbr_enable) >> >+ pps_val |= DSC_VBR_ENABLE; >> >+ else >> >+ pps_val &= ~DSC_VBR_ENABLE; >> >+ >> >+ DRM_INFO("PPS0 = 0x%08x\n", pps_val); >> >+ if (encoder->type == INTEL_OUTPUT_EDP) { >> >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val); >> >+ /* >> >+ * If 2 VDSC instances are needed, configure PPS for second >> >+ * VDSC >> >+ */ >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, >> >pps_val); >> >+ } else { >> >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), >> >pps_val); >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ >> > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), >> >+ pps_val); >> >+ } >> >+ >> >+ /* Populate PICTURE_PARAMETER_SET_1 registers */ >> >+ pps_val = 0; >> >+ pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); >> >+ DRM_INFO("PPS1 = 0x%08x\n", pps_val); >> >+ if (encoder->type == INTEL_OUTPUT_EDP) { >> >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val); >> >+ /* >> >+ * If 2 VDSC instances are needed, configure PPS for second >> >+ * VDSC >> >+ */ >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, >> >pps_val); >> >+ } else { >> >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), >> >pps_val); >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ >> > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), >> >+ pps_val); >> >+ } >> >+ >> >+ /* Populate PICTURE_PARAMETER_SET_2 registers */ >> >+ pps_val = 0; >> >+ pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | >> >+ DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); >> >+ DRM_INFO("PPS2 = 0x%08x\n", pps_val); >> >+ if (encoder->type == INTEL_OUTPUT_EDP) { >> >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); >> >+ /* >> >+ * If 2 VDSC instances are needed, configure PPS for second >> >+ * VDSC >> >+ */ >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, >> >pps_val); >> >+ } else { >> >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), >> >pps_val); >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ >> > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), >> >+ pps_val); >> >+ } >> >+ >> >+ /* Populate PICTURE_PARAMETER_SET_3 registers */ >> >+ pps_val = 0; >> >+ pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | >> >+ DSC_SLICE_WIDTH(vdsc_cfg->slice_width); >> >+ DRM_INFO("PPS3 = 0x%08x\n", pps_val); >> >+ if (encoder->type == INTEL_OUTPUT_EDP) { >> >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val); >> >+ /* >> >+ * If 2 VDSC instances are needed, configure PPS for second >> >+ * VDSC >> >+ */ >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, >> >pps_val); >> >+ } else { >> >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), >> >pps_val); >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ >> > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), >> >+ pps_val); >> >+ } >> >+ >> >+ /* Populate PICTURE_PARAMETER_SET_4 registers */ >> >+ pps_val = 0; >> >+ pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | >> >+ DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); >> >+ DRM_INFO("PPS4 = 0x%08x\n", pps_val); >> >+ if (encoder->type == INTEL_OUTPUT_EDP) { >> >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val); >> >+ /* >> >+ * If 2 VDSC instances are needed, configure PPS for second >> >+ * VDSC >> >+ */ >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, >> >pps_val); >> >+ } else { >> >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), >> >pps_val); >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ >> > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), >> >+ pps_val); >> >+ } >> >+ >> >+ /* Populate PICTURE_PARAMETER_SET_5 registers */ >> >+ pps_val = 0; >> >+ pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | >> >+ DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); >> >+ DRM_INFO("PPS5 = 0x%08x\n", pps_val); >> >+ if (encoder->type == INTEL_OUTPUT_EDP) { >> >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val); >> >+ /* >> >+ * If 2 VDSC instances are needed, configure PPS for second >> >+ * VDSC >> >+ */ >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, >> >pps_val); >> >+ } else { >> >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), >> >pps_val); >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ >> > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), >> >+ pps_val); >> >+ } >> >+ >> >+ /* Populate PICTURE_PARAMETER_SET_6 registers */ >> >+ pps_val = 0; >> >+ pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | >> >+ DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) >> >| >> >+ DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | >> >+ DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); >> >+ DRM_INFO("PPS6 = 0x%08x\n", pps_val); >> >+ if (encoder->type == INTEL_OUTPUT_EDP) { >> >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val); >> >+ /* >> >+ * If 2 VDSC instances are needed, configure PPS for second >> >+ * VDSC >> >+ */ >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, >> >pps_val); >> >+ } else { >> >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), >> >pps_val); >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ >> > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), >> >+ pps_val); >> >+ } >> >+ >> >+ /* Populate PICTURE_PARAMETER_SET_7 registers */ >> >+ pps_val = 0; >> >+ pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | >> >+ DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); >> >+ DRM_INFO("PPS7 = 0x%08x\n", pps_val); >> >+ if (encoder->type == INTEL_OUTPUT_EDP) { >> >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val); >> >+ /* >> >+ * If 2 VDSC instances are needed, configure PPS for second >> >+ * VDSC >> >+ */ >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, >> >pps_val); >> >+ } else { >> >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), >> >pps_val); >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ >> > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), >> >+ pps_val); >> >+ } >> >+ >> >+ /* Populate PICTURE_PARAMETER_SET_8 registers */ >> >+ pps_val = 0; >> >+ pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | >> >+ DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); >> >+ DRM_INFO("PPS8 = 0x%08x\n", pps_val); >> >+ if (encoder->type == INTEL_OUTPUT_EDP) { >> >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val); >> >+ /* >> >+ * If 2 VDSC instances are needed, configure PPS for second >> >+ * VDSC >> >+ */ >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, >> >pps_val); >> >+ } else { >> >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), >> >pps_val); >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ >> > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), >> >+ pps_val); >> >+ } >> >+ >> >+ /* Populate PICTURE_PARAMETER_SET_9 registers */ >> >+ pps_val = 0; >> >+ pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) | >> >+ DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); >> >+ DRM_INFO("PPS9 = 0x%08x\n", pps_val); >> >+ if (encoder->type == INTEL_OUTPUT_EDP) { >> >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val); >> >+ /* >> >+ * If 2 VDSC instances are needed, configure PPS for second >> >+ * VDSC >> >+ */ >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, >> >pps_val); >> >+ } else { >> >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), >> >pps_val); >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ >> > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), >> >+ pps_val); >> >+ } >> >+ >> >+ /* Populate PICTURE_PARAMETER_SET_10 registers */ >> >+ pps_val = 0; >> >+ pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg- >> >>rc_quant_incr_limit0) | >> >+ DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | >> >+ DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | >> >+ DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); >> >+ DRM_INFO("PPS10 = 0x%08x\n", pps_val); >> >+ if (encoder->type == INTEL_OUTPUT_EDP) { >> >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val); >> >+ /* >> >+ * If 2 VDSC instances are needed, configure PPS for second >> >+ * VDSC >> >+ */ >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, >> >pps_val); >> >+ } else { >> >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), >> >pps_val); >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ >> > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), >> >+ pps_val); >> >+ } >> >+ >> >+ /* Populate the RC_BUF_THRESH registers */ >> >+ memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); >> >+ for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { >> >+ rc_buf_thresh_dword[i/4] |= (u32)(vdsc_cfg->rc_buf_thresh[i] << >> >+ BITS_PER_BYTE * (i % 4)); >> >+ DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i, >> >+ rc_buf_thresh_dword[i/4]); >> >+ } >> >+ if (encoder->type == INTEL_OUTPUT_EDP) { >> >+ I915_WRITE(DSCA_RC_BUF_THRESH_0, >> >rc_buf_thresh_dword[0]); >> >+ I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, >> >rc_buf_thresh_dword[1]); >> >+ I915_WRITE(DSCA_RC_BUF_THRESH_1, >> >rc_buf_thresh_dword[2]); >> >+ I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, >> >rc_buf_thresh_dword[3]); >> >+ if (crtc_state->dsc_params.dsc_split) { >> >+ I915_WRITE(DSCC_RC_BUF_THRESH_0, >> >+ rc_buf_thresh_dword[0]); >> >+ I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW, >> >+ rc_buf_thresh_dword[1]); >> >+ I915_WRITE(DSCC_RC_BUF_THRESH_1, >> >+ rc_buf_thresh_dword[2]); >> >+ I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW, >> >+ rc_buf_thresh_dword[3]); >> >+ } >> >+ } else { >> >+ I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe), >> >+ rc_buf_thresh_dword[0]); >> >+ I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), >> >+ rc_buf_thresh_dword[1]); >> >+ I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe), >> >+ rc_buf_thresh_dword[2]); >> >+ I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), >> >+ rc_buf_thresh_dword[3]); >> >+ if (crtc_state->dsc_params.dsc_split) { >> >+ I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe), >> >+ rc_buf_thresh_dword[0]); >> >+ I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), >> >+ rc_buf_thresh_dword[1]); >> >+ I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe), >> >+ rc_buf_thresh_dword[2]); >> >+ I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), >> >+ rc_buf_thresh_dword[3]); >> >+ } >> >+ } >> >+ >> >+ /* Populate the RC_RANGE_PARAMETERS registers */ >> >+ memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); >> >+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { >> >+ rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg- >> >>rc_range_params[i].range_bpg_offset << >> >+ RC_BPG_OFFSET_SHIFT) | >> >+ (vdsc_cfg- >> >>rc_range_params[i].range_max_qp << >> >+ RC_MAX_QP_SHIFT) | >> >+ (vdsc_cfg- >> >>rc_range_params[i].range_min_qp << >> >+ RC_MIN_QP_SHIFT)) << 16 * >> >(i % 2)); >> >+ DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i, >> >+ rc_range_params_dword[i/2]); >> >+ } >> >+ if (encoder->type == INTEL_OUTPUT_EDP) { >> >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0, >> >+ rc_range_params_dword[0]); >> >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW, >> >+ rc_range_params_dword[1]); >> >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1, >> >+ rc_range_params_dword[2]); >> >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW, >> >+ rc_range_params_dword[3]); >> >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2, >> >+ rc_range_params_dword[4]); >> >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW, >> >+ rc_range_params_dword[5]); >> >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3, >> >+ rc_range_params_dword[6]); >> >+ I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW, >> >+ rc_range_params_dword[7]); >> >+ if (crtc_state->dsc_params.dsc_split) { >> >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0, >> >+ rc_range_params_dword[0]); >> >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW, >> >+ rc_range_params_dword[1]); >> >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1, >> >+ rc_range_params_dword[2]); >> >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW, >> >+ rc_range_params_dword[3]); >> >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2, >> >+ rc_range_params_dword[4]); >> >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW, >> >+ rc_range_params_dword[5]); >> >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3, >> >+ rc_range_params_dword[6]); >> >+ I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW, >> >+ rc_range_params_dword[7]); >> >+ } >> >+ } else { >> >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), >> >+ rc_range_params_dword[0]); >> >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), >> >+ rc_range_params_dword[1]); >> >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), >> >+ rc_range_params_dword[2]); >> >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), >> >+ rc_range_params_dword[3]); >> >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), >> >+ rc_range_params_dword[4]); >> >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), >> >+ rc_range_params_dword[5]); >> >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), >> >+ rc_range_params_dword[6]); >> >+ I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), >> >+ rc_range_params_dword[7]); >> >+ if (crtc_state->dsc_params.dsc_split) { >> >+ >> > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), >> >+ rc_range_params_dword[0]); >> >+ >> > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), >> >+ rc_range_params_dword[1]); >> >+ >> > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), >> >+ rc_range_params_dword[2]); >> >+ >> > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), >> >+ rc_range_params_dword[3]); >> >+ >> > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), >> >+ rc_range_params_dword[4]); >> >+ >> > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), >> >+ rc_range_params_dword[5]); >> >+ >> > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), >> >+ rc_range_params_dword[6]); >> >+ >> > I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), >> >+ rc_range_params_dword[7]); >> >+ } >> >+ } >> >> Any specific reason for PPS16 to be after RC_RANGE_PARAMETERS and >RC_BUF_THRESH? >> >> Anusha > >Thats just how its ordered in the bspec. Just thinking out loud, if in future, we need to use the rest of the PPS registers, then we have PPS0-10, RC_RANGE_PARAMETERS and RC_BUF_THRESH and again PPS registers.... Might be good to have all PPS registers together? But that is just a thought, left to you if you want to change the order. Patch otherwise looks good. Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Anusha >Manasi > >> >+ /* Populate Picture parameter set 16 */ >> >+ pps_val = 0; >> >+ pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | >> >+ DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / >> >num_vdsc_instances) / >> >+ vdsc_cfg->slice_width) | >> >+ DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / >> >+ vdsc_cfg->slice_height); >> >+ DRM_INFO("PPS16 = 0x%08x\n", pps_val); >> >+ if (encoder->type == INTEL_OUTPUT_EDP) { >> >+ I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val); >> >+ /* >> >+ * If 2 VDSC instances are needed, configure PPS for second >> >+ * VDSC >> >+ */ >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, >> >pps_val); >> >+ } else { >> >+ I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), >> >pps_val); >> >+ if (crtc_state->dsc_params.dsc_split) >> >+ >> > I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), >> >+ pps_val); >> >+ } >> >+} >> >+ >> >+void intel_dsc_enable(struct intel_encoder *encoder, >> >+ struct intel_crtc_state *crtc_state) { >> >+ >> >+ if (!crtc_state->dsc_params.compression_enable) >> >+ return; >> >+ >> >+ intel_configure_pps_for_dsc_encoder(encoder, crtc_state); >> >+ >> >+ return; >> >+} >> >-- >> >2.18.0 >>
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 93e57b271d3b..b49985f5d08c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3506,6 +3506,8 @@ extern void intel_rps_mark_interactive(struct drm_i915_private *i915, bool interactive); extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable); +extern void intel_dsc_enable(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state); int i915_reg_read_ioctl(struct drm_device *dev, void *data, struct drm_file *file); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4ebf7c83085c..f7cb41775c57 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5480,6 +5480,12 @@ static void intel_encoders_pre_enable(struct drm_crtc *crtc, if (encoder->pre_enable) encoder->pre_enable(encoder, crtc_state, conn_state); + + /* + * Enable and Configure Display Stream Compression in the source + * if enabled in intel_crtc_state. + */ + intel_dsc_enable(encoder, crtc_state); } } diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c index 594196a9d0f4..1f2b5dc82f16 100644 --- a/drivers/gpu/drm/i915/intel_vdsc.c +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -580,3 +580,421 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, return 0; } + +static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; + enum pipe pipe = crtc->pipe; + u32 pps_val = 0; + u32 rc_buf_thresh_dword[4]; + u32 rc_range_params_dword[8]; + u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1; + int i = 0; + + /* Populate PICTURE_PARAMETER_SET_0 registers */ + pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << + DSC_VER_MIN_SHIFT | + vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | + vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; + if (vdsc_cfg->block_pred_enable) + pps_val |= DSC_BLOCK_PREDICTION; + else + pps_val &= ~DSC_BLOCK_PREDICTION; + if (vdsc_cfg->convert_rgb) + pps_val |= DSC_COLOR_SPACE_CONVERSION; + else + pps_val &= ~DSC_COLOR_SPACE_CONVERSION; + if (vdsc_cfg->enable422) + pps_val |= DSC_422_ENABLE; + else + pps_val &= ~DSC_422_ENABLE; + if (vdsc_cfg->vbr_enable) + pps_val |= DSC_VBR_ENABLE; + else + pps_val &= ~DSC_VBR_ENABLE; + + DRM_INFO("PPS0 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_1 registers */ + pps_val = 0; + pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); + DRM_INFO("PPS1 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_2 registers */ + pps_val = 0; + pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | + DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); + DRM_INFO("PPS2 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_3 registers */ + pps_val = 0; + pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | + DSC_SLICE_WIDTH(vdsc_cfg->slice_width); + DRM_INFO("PPS3 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_4 registers */ + pps_val = 0; + pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | + DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); + DRM_INFO("PPS4 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_5 registers */ + pps_val = 0; + pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | + DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); + DRM_INFO("PPS5 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_6 registers */ + pps_val = 0; + pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) | + DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | + DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | + DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); + DRM_INFO("PPS6 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_7 registers */ + pps_val = 0; + pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | + DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); + DRM_INFO("PPS7 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_8 registers */ + pps_val = 0; + pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | + DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); + DRM_INFO("PPS8 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_9 registers */ + pps_val = 0; + pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) | + DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); + DRM_INFO("PPS9 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), + pps_val); + } + + /* Populate PICTURE_PARAMETER_SET_10 registers */ + pps_val = 0; + pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) | + DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | + DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | + DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); + DRM_INFO("PPS10 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), + pps_val); + } + + /* Populate the RC_BUF_THRESH registers */ + memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { + rc_buf_thresh_dword[i/4] |= (u32)(vdsc_cfg->rc_buf_thresh[i] << + BITS_PER_BYTE * (i % 4)); + DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i, + rc_buf_thresh_dword[i/4]); + } + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]); + I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]); + I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]); + I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]); + if (crtc_state->dsc_params.dsc_split) { + I915_WRITE(DSCC_RC_BUF_THRESH_0, + rc_buf_thresh_dword[0]); + I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW, + rc_buf_thresh_dword[1]); + I915_WRITE(DSCC_RC_BUF_THRESH_1, + rc_buf_thresh_dword[2]); + I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW, + rc_buf_thresh_dword[3]); + } + } else { + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe), + rc_buf_thresh_dword[0]); + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), + rc_buf_thresh_dword[1]); + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe), + rc_buf_thresh_dword[2]); + I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), + rc_buf_thresh_dword[3]); + if (crtc_state->dsc_params.dsc_split) { + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe), + rc_buf_thresh_dword[0]); + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), + rc_buf_thresh_dword[1]); + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe), + rc_buf_thresh_dword[2]); + I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), + rc_buf_thresh_dword[3]); + } + } + + /* Populate the RC_RANGE_PARAMETERS registers */ + memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword)); + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { + rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << + RC_BPG_OFFSET_SHIFT) | + (vdsc_cfg->rc_range_params[i].range_max_qp << + RC_MAX_QP_SHIFT) | + (vdsc_cfg->rc_range_params[i].range_min_qp << + RC_MIN_QP_SHIFT)) << 16 * (i % 2)); + DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i, + rc_range_params_dword[i/2]); + } + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0, + rc_range_params_dword[0]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW, + rc_range_params_dword[1]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1, + rc_range_params_dword[2]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW, + rc_range_params_dword[3]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2, + rc_range_params_dword[4]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW, + rc_range_params_dword[5]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3, + rc_range_params_dword[6]); + I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW, + rc_range_params_dword[7]); + if (crtc_state->dsc_params.dsc_split) { + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0, + rc_range_params_dword[0]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW, + rc_range_params_dword[1]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1, + rc_range_params_dword[2]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW, + rc_range_params_dword[3]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2, + rc_range_params_dword[4]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW, + rc_range_params_dword[5]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3, + rc_range_params_dword[6]); + I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW, + rc_range_params_dword[7]); + } + } else { + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), + rc_range_params_dword[0]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), + rc_range_params_dword[1]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), + rc_range_params_dword[2]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), + rc_range_params_dword[3]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), + rc_range_params_dword[4]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), + rc_range_params_dword[5]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), + rc_range_params_dword[6]); + I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), + rc_range_params_dword[7]); + if (crtc_state->dsc_params.dsc_split) { + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), + rc_range_params_dword[0]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), + rc_range_params_dword[1]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), + rc_range_params_dword[2]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), + rc_range_params_dword[3]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), + rc_range_params_dword[4]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), + rc_range_params_dword[5]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), + rc_range_params_dword[6]); + I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), + rc_range_params_dword[7]); + } + } + + /* Populate Picture parameter set 16 */ + pps_val = 0; + pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | + DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) / + vdsc_cfg->slice_width) | + DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / + vdsc_cfg->slice_height); + DRM_INFO("PPS16 = 0x%08x\n", pps_val); + if (encoder->type == INTEL_OUTPUT_EDP) { + I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val); + /* + * If 2 VDSC instances are needed, configure PPS for second + * VDSC + */ + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val); + } else { + I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val); + if (crtc_state->dsc_params.dsc_split) + I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), + pps_val); + } +} + +void intel_dsc_enable(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + + if (!crtc_state->dsc_params.compression_enable) + return; + + intel_configure_pps_for_dsc_encoder(encoder, crtc_state); + + return; +}
After encoder->pre_enable() hook, after link training sequence is completed, PPS registers for DSC encoder are configured using the DSC state parameters in intel_crtc_state as part of DSC enabling routine in the source. DSC enabling routine is called after encoder->pre_enable() before enbaling the pipe and after compression is enabled on the sink. v3: * Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe are used (Manasi) * Add DSC slice_row_per_frame in PPS16 (Manasi) v2: * Enable PG2 power well for VDSC on eDP Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/intel_display.c | 6 + drivers/gpu/drm/i915/intel_vdsc.c | 418 +++++++++++++++++++++++++++ 3 files changed, 426 insertions(+)