From patchwork Fri Oct 12 21:52:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10639331 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 41FCD1508 for ; Fri, 12 Oct 2018 21:52:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 407802BF80 for ; Fri, 12 Oct 2018 21:52:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 34BE52BF86; Fri, 12 Oct 2018 21:52:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9979F2BF80 for ; Fri, 12 Oct 2018 21:52:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EFD426E506; Fri, 12 Oct 2018 21:52:32 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id D8E3B6E4E4 for ; Fri, 12 Oct 2018 21:52:29 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Oct 2018 14:52:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,374,1534834800"; d="scan'208";a="80806991" Received: from josouza-mobl.jf.intel.com ([10.24.11.2]) by orsmga007.jf.intel.com with ESMTP; 12 Oct 2018 14:52:28 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Fri, 12 Oct 2018 14:52:13 -0700 Message-Id: <20181012215218.5119-11-jose.souza@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181012215218.5119-1-jose.souza@intel.com> References: <20181012215218.5119-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 11/16] drm/i915: Do not initialize display core when display is disabled X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP With display disabled, driver don't need to enable any power well or load the DMC firmware. The only thing that *_display_core_init will do when display is disabled is call intel_pch_reset_handshake(), so PCH handshake will be unset and in counterpart *_display_core_uninit() will only disable DC. The power wells enabled by BIOS during boot will be disabled in futher patch. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_runtime_pm.c | 56 ++++++++++++++++--------- 1 file changed, 36 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 3b2588a377a9..8b1c4d0db0af 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -3285,6 +3285,9 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, /* enable PCH reset handshake */ intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); + if (!INTEL_INFO(dev_priv)->num_pipes) + return; + /* enable PG1 and Misc I/O */ mutex_lock(&power_domains->lock); @@ -3296,8 +3299,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, mutex_unlock(&power_domains->lock); - if (INTEL_INFO(dev_priv)->num_pipes) - skl_init_cdclk(dev_priv); + skl_init_cdclk(dev_priv); gen9_dbuf_enable(dev_priv); @@ -3312,10 +3314,12 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv) gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + if (!INTEL_INFO(dev_priv)->num_pipes) + return; + gen9_dbuf_disable(dev_priv); - if (INTEL_INFO(dev_priv)->num_pipes) - skl_uninit_cdclk(dev_priv); + skl_uninit_cdclk(dev_priv); /* The spec doesn't call for removing the reset handshake flag */ /* disable PG1 and Misc I/O */ @@ -3352,6 +3356,9 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv, */ intel_pch_reset_handshake(dev_priv, false); + if (!INTEL_INFO(dev_priv)->num_pipes) + return; + /* Enable PG1 */ mutex_lock(&power_domains->lock); @@ -3360,8 +3367,7 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv, mutex_unlock(&power_domains->lock); - if (INTEL_INFO(dev_priv)->num_pipes) - bxt_init_cdclk(dev_priv); + bxt_init_cdclk(dev_priv); gen9_dbuf_enable(dev_priv); @@ -3376,10 +3382,12 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv) gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + if (!INTEL_INFO(dev_priv)->num_pipes) + return; + gen9_dbuf_disable(dev_priv); - if (INTEL_INFO(dev_priv)->num_pipes) - bxt_uninit_cdclk(dev_priv); + bxt_uninit_cdclk(dev_priv); /* The spec doesn't call for removing the reset handshake flag */ @@ -3475,6 +3483,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume /* 1. Enable PCH Reset Handshake */ intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); + if (!INTEL_INFO(dev_priv)->num_pipes) + return; + /* 2. Enable Comp */ val = I915_READ(CHICKEN_MISC_2); val &= ~CNL_COMP_PWR_DOWN; @@ -3502,8 +3513,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume mutex_unlock(&power_domains->lock); /* 5. Enable CD clock */ - if (INTEL_INFO(dev_priv)->num_pipes) - cnl_init_cdclk(dev_priv); + cnl_init_cdclk(dev_priv); /* 6. Enable DBUF */ gen9_dbuf_enable(dev_priv); @@ -3520,14 +3530,16 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); - /* 1. Disable all display engine functions -> aready done */ + if (!INTEL_INFO(dev_priv)->num_pipes) + return; + + /* 1. Disable all display engine functions -> already done */ /* 2. Disable DBUF */ gen9_dbuf_disable(dev_priv); /* 3. Disable CD clock */ - if (INTEL_INFO(dev_priv)->num_pipes) - cnl_uninit_cdclk(dev_priv); + cnl_uninit_cdclk(dev_priv); /* * 4. Disable Power Well 1 (PG1). @@ -3560,6 +3572,9 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, /* 1. Enable PCH reset handshake. */ intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); + if (!INTEL_INFO(dev_priv)->num_pipes) + return; + for (port = PORT_A; port <= PORT_B; port++) { /* 2. Enable DDI combo PHY comp. */ val = I915_READ(ICL_PHY_MISC(port)); @@ -3588,8 +3603,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, mutex_unlock(&power_domains->lock); /* 5. Enable CDCLK. */ - if (INTEL_INFO(dev_priv)->num_pipes) - icl_init_cdclk(dev_priv); + icl_init_cdclk(dev_priv); /* 6. Enable DBUF. */ icl_dbuf_enable(dev_priv); @@ -3610,14 +3624,16 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); - /* 1. Disable all display engine functions -> aready done */ + if (!INTEL_INFO(dev_priv)->num_pipes) + return; + + /* 1. Disable all display engine functions -> already done */ /* 2. Disable DBUF */ icl_dbuf_disable(dev_priv); /* 3. Disable CD clock */ - if (INTEL_INFO(dev_priv)->num_pipes) - icl_uninit_cdclk(dev_priv); + icl_uninit_cdclk(dev_priv); /* * 4. Disable Power Well 1 (PG1). @@ -3784,11 +3800,11 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) skl_display_core_init(dev_priv, resume); } else if (IS_GEN9_LP(dev_priv)) { bxt_display_core_init(dev_priv, resume); - } else if (IS_CHERRYVIEW(dev_priv)) { + } else if (IS_CHERRYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) { mutex_lock(&power_domains->lock); chv_phy_control_init(dev_priv); mutex_unlock(&power_domains->lock); - } else if (IS_VALLEYVIEW(dev_priv)) { + } else if (IS_VALLEYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) { mutex_lock(&power_domains->lock); vlv_cmnlane_wa(dev_priv); mutex_unlock(&power_domains->lock);