| Message ID | 20181012215218.5119-12-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/16] drm/i915: Properly set PCH as NOP when display is disabled | expand |
On Fri, 12 Oct 2018, José Roberto de Souza <jose.souza@intel.com> wrote: > With previous changes none of those warnings will be printed but lets > add then so CI can caught regressions. I like the asserts, but here too they make more sense to the casual reader as !HAS_DISPLAY. BR, Jani. > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 18 ++++++++++++++++++ > drivers/gpu/drm/i915/intel_hotplug.c | 2 ++ > 2 files changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index e7f551909bfe..92e2c7e081e5 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2029,6 +2029,8 @@ static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) > u32 hotplug_status = 0, hotplug_status_mask; > int i; > > + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); > + > if (IS_G4X(dev_priv) || > IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > hotplug_status_mask = HOTPLUG_INT_STATUS_G4X | > @@ -2067,6 +2069,8 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, > { > u32 pin_mask = 0, long_mask = 0; > > + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); > + > if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || > IS_CHERRYVIEW(dev_priv)) { > u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; > @@ -2511,6 +2515,8 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, > enum pipe pipe; > u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; > > + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); > + > if (hotplug_trigger) > ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk); > > @@ -2557,6 +2563,8 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, > enum pipe pipe; > u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; > > + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); > + > if (hotplug_trigger) > ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb); > > @@ -2725,6 +2733,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) > u32 iir; > enum pipe pipe; > > + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); > + > if (master_ctl & GEN8_DE_MISC_IRQ) { > iir = I915_READ(GEN8_DE_MISC_IIR); > if (iir) { > @@ -3875,6 +3885,8 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) > { > u32 hotplug_irqs, enabled_irqs; > > + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); > + > hotplug_irqs = SDE_HOTPLUG_MASK_SPT; > enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt); > > @@ -3903,6 +3915,8 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) > { > u32 hotplug_irqs, enabled_irqs; > > + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); > + > if (INTEL_GEN(dev_priv) >= 8) { > hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; > enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw); > @@ -3965,6 +3979,8 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) > { > u32 hotplug_irqs, enabled_irqs; > > + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); > + > enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt); > hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK; > > @@ -4682,6 +4698,8 @@ static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv) > { > u32 hotplug_en; > > + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); > + > lockdep_assert_held(&dev_priv->irq_lock); > > /* Note HDMI and DP share hotplug bits */ > diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c > index 648a13c6043c..908d8e589f9a 100644 > --- a/drivers/gpu/drm/i915/intel_hotplug.c > +++ b/drivers/gpu/drm/i915/intel_hotplug.c > @@ -399,6 +399,8 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, > if (!pin_mask) > return; > > + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); > + > spin_lock(&dev_priv->irq_lock); > for_each_intel_encoder(&dev_priv->drm, encoder) { > enum hpd_pin pin = encoder->hpd_pin;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index e7f551909bfe..92e2c7e081e5 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2029,6 +2029,8 @@ static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) u32 hotplug_status = 0, hotplug_status_mask; int i; + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); + if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) hotplug_status_mask = HOTPLUG_INT_STATUS_G4X | @@ -2067,6 +2069,8 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv, { u32 pin_mask = 0, long_mask = 0; + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); + if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; @@ -2511,6 +2515,8 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe; u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); + if (hotplug_trigger) ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk); @@ -2557,6 +2563,8 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe; u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); + if (hotplug_trigger) ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb); @@ -2725,6 +2733,8 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) u32 iir; enum pipe pipe; + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); + if (master_ctl & GEN8_DE_MISC_IRQ) { iir = I915_READ(GEN8_DE_MISC_IIR); if (iir) { @@ -3875,6 +3885,8 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv) { u32 hotplug_irqs, enabled_irqs; + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); + hotplug_irqs = SDE_HOTPLUG_MASK_SPT; enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt); @@ -3903,6 +3915,8 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) { u32 hotplug_irqs, enabled_irqs; + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); + if (INTEL_GEN(dev_priv) >= 8) { hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw); @@ -3965,6 +3979,8 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv) { u32 hotplug_irqs, enabled_irqs; + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); + enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt); hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK; @@ -4682,6 +4698,8 @@ static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv) { u32 hotplug_en; + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); + lockdep_assert_held(&dev_priv->irq_lock); /* Note HDMI and DP share hotplug bits */ diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c index 648a13c6043c..908d8e589f9a 100644 --- a/drivers/gpu/drm/i915/intel_hotplug.c +++ b/drivers/gpu/drm/i915/intel_hotplug.c @@ -399,6 +399,8 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, if (!pin_mask) return; + WARN_ON_ONCE(!INTEL_INFO(dev_priv)->num_pipes); + spin_lock(&dev_priv->irq_lock); for_each_intel_encoder(&dev_priv->drm, encoder) { enum hpd_pin pin = encoder->hpd_pin;
With previous changes none of those warnings will be printed but lets add then so CI can caught regressions. Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 18 ++++++++++++++++++ drivers/gpu/drm/i915/intel_hotplug.c | 2 ++ 2 files changed, 20 insertions(+)