From patchwork Fri Oct 12 21:52:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10639335 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE1A31508 for ; Fri, 12 Oct 2018 21:52:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC80C2BF80 for ; Fri, 12 Oct 2018 21:52:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D110B2BF86; Fri, 12 Oct 2018 21:52:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7E5E22BF80 for ; Fri, 12 Oct 2018 21:52:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 758E26E50C; Fri, 12 Oct 2018 21:52:33 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1C00A6E4E4 for ; Fri, 12 Oct 2018 21:52:30 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Oct 2018 14:52:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,374,1534834800"; d="scan'208";a="80807004" Received: from josouza-mobl.jf.intel.com ([10.24.11.2]) by orsmga007.jf.intel.com with ESMTP; 12 Oct 2018 14:52:28 -0700 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Fri, 12 Oct 2018 14:52:17 -0700 Message-Id: <20181012215218.5119-15-jose.souza@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181012215218.5119-1-jose.souza@intel.com> References: <20181012215218.5119-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 15/16] drm/i915: Power down any power well left on by BIOS X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Just not enable power wells is not enough as BIOS/firmware can turn on some power wells during boot, so is needed disable those to save power and to avoid mismatch state errors in intel_power_domains_verify_state(). So here disabling every non-real power well first as it could have some dependency in a real power well and then disabling all power wells in reverse(power well 2 depends on power well 1 and so on) other as required by spec. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_runtime_pm.c | 59 +++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 56c65d921acd..0f5016b74228 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -3785,6 +3785,61 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv); +static void +intel_power_domains_disable_leftovers(struct drm_i915_private *dev_priv) +{ + struct i915_power_domains *power_domains = &dev_priv->power_domains; + struct i915_power_well *power_well; + int i; + + mutex_lock(&power_domains->lock); + + /* Disable everything that is enabled and is not a HW power_well */ + for_each_power_well(dev_priv, power_well) { + WARN_ON(power_well->count); + + /* + * Power wells not belonging to any domain (like the MISC_IO + * and PW1 power wells) are under FW control, so ignore them, + * since their state can change asynchronously. + */ + if (!power_well->desc->domains || power_well->desc->always_on) + continue; + + if (power_well->desc->id != DISP_PW_ID_NONE) + continue; + + if (!power_well->hw_enabled) + continue; + + intel_power_well_disable(dev_priv, power_well); + } + + /* Disabled HW power wells in reverse order, so power well 2 is + * disabled before power well 1 and so on as required by spec. + */ + for (i = power_domains->power_well_count - 1; i >= 0; i--) { + power_well = &power_domains->power_wells[i]; + + WARN_ON(power_well->count); + + if (!power_well->desc->domains || power_well->desc->always_on) + continue; + + if (power_well->desc->id == DISP_PW_ID_NONE) + continue; + + if (!power_well->hw_enabled) + continue; + + intel_power_well_disable(dev_priv, power_well); + } + + mutex_unlock(&power_domains->lock); + + intel_power_domains_verify_state(dev_priv); +} + /** * intel_power_domains_init_hw - initialize hardware power domain state * @dev_priv: i915 device instance @@ -3838,6 +3893,10 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); intel_power_domains_sync_hw(dev_priv); + /* Disable everything left enabled by BIOS/firmware */ + if (!INTEL_INFO(dev_priv)->num_pipes) + intel_power_domains_disable_leftovers(dev_priv); + power_domains->initializing = false; }