Message ID | 20181017200554.20868-1-michal.wajdeczko@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v2,1/2] drm/i915/guc: Limit number of scratch registers used for H2G | expand |
On 17/10/18 13:05, Michal Wajdeczko wrote: > We wrongly assumed that GuC is only using last scratch register > for G2H messages, but in fact it is also using register [14] to > report sleep state status. Remove that register from our H2G > send registers pool. > > v2: No message from host to GuC uses more than 8 registers and > the GuC FW itself uses an 8-element array to store the H2G message, > so we may reduce our send array to just 8 registers (Daniele) > > Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/intel_guc.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c > index 4c61eb9..390ae7e 100644 > --- a/drivers/gpu/drm/i915/intel_guc.c > +++ b/drivers/gpu/drm/i915/intel_guc.c > @@ -50,7 +50,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc) > unsigned int i; > > guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0)); > - guc->send_regs.count = SOFT_SCRATCH_COUNT - 1; > + guc->send_regs.count = 8; > + GEM_BUG_ON(guc->send_regs.count > SOFT_SCRATCH_COUNT); With the info about no command using more than 8 regs added to the code as a comment: Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> nitpick: if we add a define instead of using "8" directly we can ditch the GEM_BUG_ON in favor of a BUILD_BUG_ON. If you do that, the comment probably belongs with the define. Thanks, Daniele > > for (i = 0; i < guc->send_regs.count; i++) { > fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, >
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 4c61eb9..390ae7e 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -50,7 +50,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc) unsigned int i; guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0)); - guc->send_regs.count = SOFT_SCRATCH_COUNT - 1; + guc->send_regs.count = 8; + GEM_BUG_ON(guc->send_regs.count > SOFT_SCRATCH_COUNT); for (i = 0; i < guc->send_regs.count; i++) { fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
We wrongly assumed that GuC is only using last scratch register for G2H messages, but in fact it is also using register [14] to report sleep state status. Remove that register from our H2G send registers pool. v2: No message from host to GuC uses more than 8 registers and the GuC FW itself uses an 8-element array to store the H2G message, so we may reduce our send array to just 8 registers (Daniele) Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/intel_guc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)