From patchwork Thu Oct 18 15:28:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10647509 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A416217DE for ; Thu, 18 Oct 2018 15:28:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9621A28D97 for ; Thu, 18 Oct 2018 15:28:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8AD4B28D9F; Thu, 18 Oct 2018 15:28:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 342EC28D97 for ; Thu, 18 Oct 2018 15:28:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 321206E090; Thu, 18 Oct 2018 15:28:41 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1BA376E00E for ; Thu, 18 Oct 2018 15:28:33 +0000 (UTC) Received: by mail-wm1-x344.google.com with SMTP id o17-v6so27944wmh.0 for ; Thu, 18 Oct 2018 08:28:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hNe1CSdyen8y0gdzAy8S59EArkMzd+2lLtc42KDzZH0=; b=kipcJXPuyObxTN+NHlAQOvyk8XdyjlSBAK+DO2w5QaAADXmzPjKldOOhA7E+NkIt2n JntBDnIlqoG7AXQm1C2k7A3Ym2lb2lGTMJEqpw3YfPMVI/aZbvBjqnE/QSXMJRCYrTQS GvEkZYvgFK1oGidcpYY7sBcTI65u3ubsME1cBSW0YF413BPme0CwQr8pYD+d9OQizSTS F+ZJOMadaJJ4cFGRMUX//h/hA/2UDBdcjI2/m3bMhPxgxfq8/ZWxvZDfFK6uDADiMDyF wQjkSQ6iwbpKdxEYHi+6ppXWMY22R/Uxdcrczvm8mAGJNI/uQEQ3LIPgtUvGhTqb6cJq k7Zg== X-Gm-Message-State: ABuFfoje2f1CiqYvv6B4Fx1bn2BCf2j3vrs8iNmWCcZDDf0iVUUrxwJf knbFZxbckVA6trb8IkkBOZriCA== X-Google-Smtp-Source: ACcGV63huCHJC+VVc4W91YiOsMs3BWguMubEzDNqOqpvM4CqiTrggzhLMAdp7/77sdIij5VGhEqd/w== X-Received: by 2002:a1c:9816:: with SMTP id a22-v6mr802333wme.13.1539876511658; Thu, 18 Oct 2018 08:28:31 -0700 (PDT) Received: from localhost.localdomain ([91.110.193.16]) by smtp.gmail.com with ESMTPSA id i6-v6sm19530387wrq.4.2018.10.18.08.28.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 18 Oct 2018 08:28:31 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: igt-dev@lists.freedesktop.org Date: Thu, 18 Oct 2018 16:28:07 +0100 Message-Id: <20181018152815.31816-10-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181018152815.31816-1-tvrtko.ursulin@linux.intel.com> References: <20181018152815.31816-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH i-g-t 09/17] gem_wsim: Submit fence support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Intel-gfx@lists.freedesktop.org MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Add support for submit fences in a way similar to how normal input fences are handled. Eg: 1.RCS.500-1000.0.0 1.VCS1.3000.s-1.0 1.VCS2.3000.s-2.0 Submit fences are signalled when the originating request enters the submission backend. Signed-off-by: Tvrtko Ursulin --- benchmarks/gem_wsim.c | 20 ++++++++++++++++---- benchmarks/wsim/README | 17 +++++++++++++++++ 2 files changed, 33 insertions(+), 4 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 0010f46c357d..a77a322ee309 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -86,6 +86,7 @@ enum w_type struct deps { int nr; + bool submit_fence; int *list; }; @@ -254,17 +255,23 @@ parse_dependencies(unsigned int nr_steps, struct w_step *w, char *_desc) w->data_deps.list == w->fence_deps.list); while ((token = strtok_r(tstart, "/", &tctx)) != NULL) { + bool submit_fence = false; char *str = token; struct deps *deps; int dep; tstart = NULL; - if (strlen(token) > 1 && token[0] == 'f') { + if (str[0] == '-' || (str[0] >= '0' && str[0] <= '9')) { + deps = &w->data_deps; + } else { + if (str[0] == 's') + submit_fence = true; + else if (str[0] != 'f') + return -1; + deps = &w->fence_deps; str++; - } else { - deps = &w->data_deps; } dep = atoi(str); @@ -282,6 +289,7 @@ parse_dependencies(unsigned int nr_steps, struct w_step *w, char *_desc) sizeof(*deps->list) * deps->nr); igt_assert(deps->list); deps->list[deps->nr - 1] = dep; + deps->submit_fence = submit_fence; } } @@ -1891,7 +1899,11 @@ do_eb(struct workload *wrk, struct w_step *w, enum intel_engine_id engine, igt_assert(tgt >= 0 && tgt < w->idx); igt_assert(wrk->steps[tgt].emit_fence > 0); - w->eb.flags |= I915_EXEC_FENCE_IN; + if (w->fence_deps.submit_fence) + w->eb.flags |= I915_EXEC_FENCE_SUBMIT; + else + w->eb.flags |= I915_EXEC_FENCE_IN; + w->eb.rsvd2 = wrk->steps[tgt].emit_fence; } diff --git a/benchmarks/wsim/README b/benchmarks/wsim/README index 205cd6c93afb..4786f116b4ac 100644 --- a/benchmarks/wsim/README +++ b/benchmarks/wsim/README @@ -114,6 +114,23 @@ runnable. When the second RCS batch completes the standalone fence is signaled which allows the two VCS batches to be executed. Finally we wait until the both VCS batches have completed before starting the (optional) next iteration. +Submit fences +------------- + +Submit fences are a type of input fence which are signalled when the originating +batch buffer is submitted to the GPU. (In contrary to normal sync fences, which +are signalled when completed.) + +Submit fences have the identical syntax as the sync fences with the lower-case +'s' being used to select them. Eg: + + 1.RCS.500-1000.0.0 + 1.VCS1.3000.s-1.0 + 1.VCS2.3000.s-2.0 + +Here VCS1 and VCS2 batches will only be submitted for executing once the RCS +batch enters the GPU. + Context priority ----------------