diff mbox series

[v2,2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook

Message ID 20181023191248.26418-2-manasi.d.navare@intel.com (mailing list archive)
State New, archived
Headers show
Series [v2,1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits | expand

Commit Message

Navare, Manasi Oct. 23, 2018, 7:12 p.m. UTC 
In case of Legacy DP connector on TypeC port, the
flex IO DPMLE register is set to number of lanes configured
by the display driver which will be programmed into DDI_BUF_CTL
PORT_WIDTH_SELECTION.
This needs to be programmed before enabling the shared PLLs hence
add a pre_pll_enable hook for ICL and add this programming in that hook.

v2:
* Remove the check for combophy port (Jose)
* Simplify the port reversal check logic (Jose)

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jose Roberto de Souza <jose.souza@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 49 ++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

Comments

Imre Deak Oct. 31, 2018, 6:40 p.m. UTC | #1 
On Tue, Oct 23, 2018 at 12:12:48PM -0700, Manasi Navare wrote:
> In case of Legacy DP connector on TypeC port, the
> flex IO DPMLE register is set to number of lanes configured
> by the display driver which will be programmed into DDI_BUF_CTL
> PORT_WIDTH_SELECTION.
> This needs to be programmed before enabling the shared PLLs hence
> add a pre_pll_enable hook for ICL and add this programming in that hook.
> 
> v2:
> * Remove the check for combophy port (Jose)
> * Simplify the port reversal check logic (Jose)
> 
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Jose Roberto de Souza <jose.souza@intel.com>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

Looks ok:
Acked-by: Imre Deak <imre.deak@intel.com>

Manasi, are you going to merge this? I could rebase my patchset after
that.

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 49 ++++++++++++++++++++++++++++++++
>  1 file changed, 49 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 6b9742baa5f2..246424605768 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3311,6 +3311,53 @@ static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
>  	bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
>  }
>  
> +static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
> +					 const struct intel_crtc_state *pipe_config,
> +					 enum port port)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> +	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> +	u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
> +	bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> +
> +	val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
> +	switch (pipe_config->lane_count) {
> +	case 1:
> +		val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
> +		DFLEXDPMLE1_DPMLETC_ML0(tc_port);
> +		break;
> +	case 2:
> +		val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
> +		DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
> +		break;
> +	case 4:
> +		val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
> +		break;
> +	default:
> +		MISSING_CASE(pipe_config->lane_count);
> +	}
> +	I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
> +}
> +
> +static void icl_ddi_pre_pll_enable(struct intel_encoder *encoder,
> +				   const struct intel_crtc_state *pipe_config,
> +				   const struct drm_connector_state *conn_state)
> +{
> +	enum port port = encoder->port;
> +	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> +
> +	/*
> +	 * Program the lane count for static/dynamic connections on Type-C ports.
> +	 * Skip this step for TBT.
> +	 */
> +	if (dig_port->tc_type == TC_PORT_UNKNOWN ||
> +	    dig_port->tc_type == TC_PORT_TBT)
> +		return;
> +
> +	intel_ddi_set_fia_lane_count(encoder, pipe_config, port);
> +}
> +
>  void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> @@ -3828,6 +3875,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>  	intel_encoder->enable = intel_enable_ddi;
>  	if (IS_GEN9_LP(dev_priv))
>  		intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
> +	if (IS_ICELAKE(dev_priv))
> +		intel_encoder->pre_pll_enable = icl_ddi_pre_pll_enable;
>  	intel_encoder->pre_enable = intel_ddi_pre_enable;
>  	intel_encoder->disable = intel_disable_ddi;
>  	intel_encoder->post_disable = intel_ddi_post_disable;
> -- 
> 2.18.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Navare, Manasi Oct. 31, 2018, 11:37 p.m. UTC | #2 
Pushed to dinq, thanks for the patch and reviews

Manasi

On Tue, Oct 23, 2018 at 12:12:48PM -0700, Manasi Navare wrote:
> In case of Legacy DP connector on TypeC port, the
> flex IO DPMLE register is set to number of lanes configured
> by the display driver which will be programmed into DDI_BUF_CTL
> PORT_WIDTH_SELECTION.
> This needs to be programmed before enabling the shared PLLs hence
> add a pre_pll_enable hook for ICL and add this programming in that hook.
> 
> v2:
> * Remove the check for combophy port (Jose)
> * Simplify the port reversal check logic (Jose)
> 
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Jose Roberto de Souza <jose.souza@intel.com>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 49 ++++++++++++++++++++++++++++++++
>  1 file changed, 49 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 6b9742baa5f2..246424605768 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3311,6 +3311,53 @@ static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
>  	bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
>  }
>  
> +static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
> +					 const struct intel_crtc_state *pipe_config,
> +					 enum port port)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> +	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> +	u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
> +	bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> +
> +	val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
> +	switch (pipe_config->lane_count) {
> +	case 1:
> +		val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
> +		DFLEXDPMLE1_DPMLETC_ML0(tc_port);
> +		break;
> +	case 2:
> +		val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
> +		DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
> +		break;
> +	case 4:
> +		val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
> +		break;
> +	default:
> +		MISSING_CASE(pipe_config->lane_count);
> +	}
> +	I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
> +}
> +
> +static void icl_ddi_pre_pll_enable(struct intel_encoder *encoder,
> +				   const struct intel_crtc_state *pipe_config,
> +				   const struct drm_connector_state *conn_state)
> +{
> +	enum port port = encoder->port;
> +	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> +
> +	/*
> +	 * Program the lane count for static/dynamic connections on Type-C ports.
> +	 * Skip this step for TBT.
> +	 */
> +	if (dig_port->tc_type == TC_PORT_UNKNOWN ||
> +	    dig_port->tc_type == TC_PORT_TBT)
> +		return;
> +
> +	intel_ddi_set_fia_lane_count(encoder, pipe_config, port);
> +}
> +
>  void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> @@ -3828,6 +3875,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>  	intel_encoder->enable = intel_enable_ddi;
>  	if (IS_GEN9_LP(dev_priv))
>  		intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
> +	if (IS_ICELAKE(dev_priv))
> +		intel_encoder->pre_pll_enable = icl_ddi_pre_pll_enable;
>  	intel_encoder->pre_enable = intel_ddi_pre_enable;
>  	intel_encoder->disable = intel_disable_ddi;
>  	intel_encoder->post_disable = intel_ddi_post_disable;
> -- 
> 2.18.0
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6b9742baa5f2..246424605768 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3311,6 +3311,53 @@  static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
 	bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
 }
 
+static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
+					 const struct intel_crtc_state *pipe_config,
+					 enum port port)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+	u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
+	bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+
+	val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
+	switch (pipe_config->lane_count) {
+	case 1:
+		val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
+		DFLEXDPMLE1_DPMLETC_ML0(tc_port);
+		break;
+	case 2:
+		val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
+		DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
+		break;
+	case 4:
+		val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
+		break;
+	default:
+		MISSING_CASE(pipe_config->lane_count);
+	}
+	I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
+}
+
+static void icl_ddi_pre_pll_enable(struct intel_encoder *encoder,
+				   const struct intel_crtc_state *pipe_config,
+				   const struct drm_connector_state *conn_state)
+{
+	enum port port = encoder->port;
+	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+
+	/*
+	 * Program the lane count for static/dynamic connections on Type-C ports.
+	 * Skip this step for TBT.
+	 */
+	if (dig_port->tc_type == TC_PORT_UNKNOWN ||
+	    dig_port->tc_type == TC_PORT_TBT)
+		return;
+
+	intel_ddi_set_fia_lane_count(encoder, pipe_config, port);
+}
+
 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
@@ -3828,6 +3875,8 @@  void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	intel_encoder->enable = intel_enable_ddi;
 	if (IS_GEN9_LP(dev_priv))
 		intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
+	if (IS_ICELAKE(dev_priv))
+		intel_encoder->pre_pll_enable = icl_ddi_pre_pll_enable;
 	intel_encoder->pre_enable = intel_ddi_pre_enable;
 	intel_encoder->disable = intel_disable_ddi;
 	intel_encoder->post_disable = intel_ddi_post_disable;