@@ -639,6 +639,7 @@ struct i915_psr {
ktime_t last_entry_attempt;
ktime_t last_exit;
u32 irq_aux_error;
+ bool sink_not_reliable;
};
enum intel_pch {
@@ -542,6 +542,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
}
+ if (dev_priv->psr.sink_not_reliable) {
+ DRM_DEBUG_KMS("Sink not reliable set\n");
+ return;
+ }
+
if (IS_HASWELL(dev_priv) &&
I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &
S3D_ENABLE) {
@@ -942,6 +947,7 @@ static void intel_psr_handle_irq(struct drm_i915_private *dev_priv)
mutex_lock(&psr->lock);
intel_psr_disable_locked(psr->dp);
+ psr->sink_not_reliable = true;
/* let's make sure that sink is awaken */
drm_dp_dpcd_writeb(&psr->dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
@@ -1141,6 +1147,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) {
DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");
intel_psr_disable_locked(intel_dp);
+ psr->sink_not_reliable = true;
}
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) {
@@ -1158,8 +1165,10 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
if (val & ~errors)
DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n",
val & ~errors);
- if (val & errors)
+ if (val & errors) {
intel_psr_disable_locked(intel_dp);
+ psr->sink_not_reliable = true;
+ }
/* clear status register */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);
exit:
When we detect a error and disable PSR, it is kept disable until the next modeset but as the sink already show signs that it do not properly work with PSR lets disabled it for good to avoid any additional flickering. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 11 ++++++++++- 2 files changed, 11 insertions(+), 1 deletion(-)