From patchwork Fri Oct 26 04:49:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 10656923 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AB9B114DE for ; Fri, 26 Oct 2018 04:55:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9AE242C5B6 for ; Fri, 26 Oct 2018 04:55:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8F2EA2C5C7; Fri, 26 Oct 2018 04:55:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3CA042C5B6 for ; Fri, 26 Oct 2018 04:55:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1B4656E3FC; Fri, 26 Oct 2018 04:55:58 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6AECF6E3EE for ; Fri, 26 Oct 2018 04:55:39 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Oct 2018 21:55:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,426,1534834800"; d="scan'208";a="244494118" Received: from anusha.jf.intel.com ([10.7.198.74]) by orsmga004.jf.intel.com with ESMTP; 25 Oct 2018 21:55:39 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Thu, 25 Oct 2018 21:49:39 -0700 Message-Id: <20181026044943.29334-4-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181026044943.29334-1-anusha.srivatsa@intel.com> References: <20181026044943.29334-1-anusha.srivatsa@intel.com> Subject: [Intel-gfx] [v3 3/7] i915/dp/fec: Check for FEC Support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dhinakaran Pandiyan MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP For DP 1.4 and above, Display Stream compression can be enabled only if Forward Error Correctin can be performed. Check if the sink supports FEC using the helper. v2: Mention External DP where ever FEC is mentioned in the code.Check return status of dpcd reads. (Gaurav) - Do regular mode check even if FEC is not supported. (manasi) v3: Do not perform any dpcd writes in the atomic check phase. (DK, Manasi) v4: Use debug level logging for scenario where sink does not support a feature. (DK) v5: Correct commit message. rebase. v6: pass single field instead of an array for helper function. (manasi) Cc: Gaurav K Singh Cc: Ville Syrjala Cc: Jani Nikula Cc: Manasi Navare Cc: Dhinakaran Pandiyan Signed-off-by: Anusha Srivatsa Reviewed-by: Manasi Navare --- drivers/gpu/drm/i915/intel_dp.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 16d1db7c9398..cfcef9e4b5d9 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -680,7 +680,7 @@ intel_dp_mode_valid(struct drm_connector *connector, dsc_slice_count = drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, true); - } else { + } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { dsc_max_output_bpp = intel_dp_dsc_get_output_bpp(max_link_clock, max_lanes, @@ -690,7 +690,8 @@ intel_dp_mode_valid(struct drm_connector *connector, intel_dp_dsc_get_slice_count(intel_dp, target_clock, mode->hdisplay); - } + } else + DRM_DEBUG_KMS("Sink device does not Support FEC\n"); } if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) || @@ -2063,6 +2064,13 @@ static bool intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (pipe == PIPE_A && !intel_dp_is_edp(intel_dp)) return false; + /* DSC not supported if external DP sink does not support FEC */ + if (!intel_dp_is_edp(intel_dp) && + !drm_dp_sink_supports_fec(intel_dp->fec_capable)) { + DRM_DEBUG_KMS("Sink does not support Forward Error Correction, disabling Display Compression\n"); + return false; + } + /* DSC not supported for DSC sink BPC < 8 */ if (limits->max_bpp < 3 * DP_DSC_MIN_SUPPORTED_BPC) { DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");