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[84.106.84.65]) by smtp.gmail.com with ESMTPSA id e8-v6sm3502376eje.4.2018.11.02.04.44.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 02 Nov 2018 04:44:50 -0700 (PDT) From: Hans de Goede X-Google-Original-From: Hans de Goede To: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= , Daniel Vetter Date: Fri, 2 Nov 2018 12:44:47 +0100 Message-Id: <20181102114447.29501-1-hdegoede@redhat.com> X-Mailer: git-send-email 2.19.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915: intel_pipe_config_compare: Don't compare DSI PLL regs when adjusting X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hans de Goede , intel-gfx , dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The GOP sometimes initializes the DSI pclk at a (slightly) different freq then the pclk which we pick. intel_pipe_config_compare() allows for this by doing a fuzzy compare on the port_clock. But the pclk difference not only results in the port_clock and base.adjusted_mode.crtc_clock clocks being a bit different, but also in us picking different dsi_pll register values matching the different pclk. This commit makes us only do the dsi_pll register compare when the adjust parameter is false, so only from verify_crtc_state(), so that we correctly do a fast modeset at boot avoiding the screen going black for about 1 sec. Signed-off-by: Hans de Goede --- drivers/gpu/drm/i915/intel_display.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b219d5858160..82fa85df0fba 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11759,8 +11759,10 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); - PIPE_CONF_CHECK_X(dsi_pll.ctrl); - PIPE_CONF_CHECK_X(dsi_pll.div); + if (!adjust) { + PIPE_CONF_CHECK_X(dsi_pll.ctrl); + PIPE_CONF_CHECK_X(dsi_pll.div); + } if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) PIPE_CONF_CHECK_I(pipe_bpp);