From patchwork Fri Nov 9 14:44:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 10676113 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 844595A4 for ; Fri, 9 Nov 2018 14:45:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6846A2ECBB for ; Fri, 9 Nov 2018 14:45:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5B86F2ECCA; Fri, 9 Nov 2018 14:45:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D529C2ECBB for ; Fri, 9 Nov 2018 14:45:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 61BF26E678; Fri, 9 Nov 2018 14:45:12 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 63B516E678 for ; Fri, 9 Nov 2018 14:45:11 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Nov 2018 06:45:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,483,1534834800"; d="scan'208";a="85285853" Received: from rosetta.fi.intel.com ([10.237.72.186]) by fmsmga008.fm.intel.com with ESMTP; 09 Nov 2018 06:45:09 -0800 Received: by rosetta.fi.intel.com (Postfix, from userid 1000) id BFE0684082C; Fri, 9 Nov 2018 16:44:54 +0200 (EET) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Fri, 9 Nov 2018 16:44:54 +0200 Message-Id: <20181109144454.31143-1-mika.kuoppala@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181109140924.2663-2-mika.kuoppala@linux.intel.com> References: <20181109140924.2663-2-mika.kuoppala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Request no slices if no active pipes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rodrigo Vivi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Skip the hardware dbuf slice update if we don't have active pipes. With no active pipes, we don't have powerwell and thus programming the dbuf slice counts leads to accessing hardware without runtime pm ref. v2: bugzilla tag (Imre) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108654 Cc: Imre Deak Cc: Ville Syrjälä Cc: Rodrigo Vivi Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_display.c | 32 +++++++++++++++---------- drivers/gpu/drm/i915/intel_drv.h | 3 +-- drivers/gpu/drm/i915/intel_runtime_pm.c | 12 ++++++++-- 3 files changed, 30 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 05125c7c2aa1..0514b89611ac 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12644,23 +12644,23 @@ static void skl_update_crtcs(struct drm_atomic_state *state) struct intel_crtc *intel_crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; struct intel_crtc_state *cstate; - unsigned int updated = 0; + unsigned int updated = 0, active_count = 0; + u8 required_slices; bool progress; enum pipe pipe; int i; - u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices; - u8 required_slices = intel_state->wm_results.ddb.enabled_slices; - const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {}; - for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { /* ignore allocations for crtc's that have been turned off. */ - if (new_crtc_state->active) + if (new_crtc_state->active) { + active_count++; entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; + } + } - /* If 2nd DBuf slice required, enable it here */ - if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices) - icl_dbuf_slices_update(dev_priv, required_slices); + required_slices = active_count ? intel_state->wm_results.ddb.enabled_slices : 0; + intel_dbuf_slices_update(dev_priv, required_slices); /* * Whenever the number of active pipes changes, we need to make sure we @@ -12670,6 +12670,7 @@ static void skl_update_crtcs(struct drm_atomic_state *state) */ do { progress = false; + active_count = 0; for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { bool vbl_wait = false; @@ -12679,7 +12680,12 @@ static void skl_update_crtcs(struct drm_atomic_state *state) cstate = to_intel_crtc_state(new_crtc_state); pipe = intel_crtc->pipe; - if (updated & cmask || !cstate->base.active) + if (!cstate->base.active) + continue; + + active_count++; + + if (updated & cmask) continue; if (skl_ddb_allocation_overlaps(dev_priv, @@ -12713,9 +12719,9 @@ static void skl_update_crtcs(struct drm_atomic_state *state) } } while (progress); - /* If 2nd DBuf slice is no more required disable it */ - if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices) - icl_dbuf_slices_update(dev_priv, required_slices); + + required_slices = active_count ? intel_state->wm_results.ddb.enabled_slices : 0; + intel_dbuf_slices_update(dev_priv, required_slices); } static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 21819a9bdcae..d643f8877097 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -2086,8 +2086,7 @@ bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, enum intel_display_power_domain domain); void intel_display_power_put(struct drm_i915_private *dev_priv, enum intel_display_power_domain domain); -void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, - u8 req_slices); +void intel_dbuf_slices_update(struct drm_i915_private *dev_priv, u8 req_slices); static inline void assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 770de2632530..3a271ac22fec 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -3233,8 +3233,8 @@ static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv) return 2; } -void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, - u8 req_slices) +static void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, + const u8 req_slices) { const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices; bool ret; @@ -3256,6 +3256,14 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices; } +void intel_dbuf_slices_update(struct drm_i915_private *dev_priv, u8 slices) +{ + if (INTEL_GEN(dev_priv) < 11) + return; + + icl_dbuf_slices_update(dev_priv, slices); +} + static void icl_dbuf_enable(struct drm_i915_private *dev_priv) { I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);