From patchwork Mon Nov 12 17:12:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10679057 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D745E139B for ; Mon, 12 Nov 2018 17:13:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E580E2A2CD for ; Mon, 12 Nov 2018 17:12:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D9A692A350; Mon, 12 Nov 2018 17:12:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00,HK_RANDOM_FROM, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0C4892A000 for ; Mon, 12 Nov 2018 17:12:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C3D366E0B2; Mon, 12 Nov 2018 17:12:57 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9005A6E0A5 for ; Mon, 12 Nov 2018 17:12:56 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Nov 2018 09:12:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,496,1534834800"; d="scan'208";a="105598655" Received: from scygan-mobl.ger.corp.intel.com (HELO localhost.localdomain) ([10.252.10.123]) by fmsmga004.fm.intel.com with ESMTP; 12 Nov 2018 09:12:55 -0800 From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Mon, 12 Nov 2018 17:12:42 +0000 Message-Id: <20181112171242.7640-8-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181112171242.7640-1-tvrtko.ursulin@linux.intel.com> References: <20181112171242.7640-1-tvrtko.ursulin@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 7/7] drm/i915: Remove double underscore from static device info member names X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Now that the device info data is truly const and all call sites have been converted we can rely on read-only protection to notify us of any mistakes. Signed-off-by: Tvrtko Ursulin Cc: Chris Wilson Cc: Jani Nikula --- Or it may be a good idea to leave the double underscore in for protecting the in flight patches or in fact any future work. --- drivers/gpu/drm/i915/i915_drv.c | 18 ++-- drivers/gpu/drm/i915/i915_pci.c | 114 +++++++++++------------ drivers/gpu/drm/i915/intel_device_info.c | 2 +- drivers/gpu/drm/i915/intel_device_info.h | 16 ++-- 4 files changed, 75 insertions(+), 75 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 14c199438978..83e711b9f2f7 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1668,14 +1668,14 @@ i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) * Copy over entries that are both set statically but can also be * modified at runtime. */ - runtime_info->gen = device_info->__gen; - runtime_info->has_fbc = device_info->__has_fbc; - runtime_info->has_rc6 = device_info->__has_rc6; - runtime_info->has_rc6p = device_info->__has_rc6p; - runtime_info->ppgtt = device_info->__ppgtt; - runtime_info->page_sizes = device_info->__page_sizes; - runtime_info->ring_mask = device_info->__ring_mask; - runtime_info->num_pipes = device_info->__num_pipes; + runtime_info->gen = device_info->gen; + runtime_info->has_fbc = device_info->has_fbc; + runtime_info->has_rc6 = device_info->has_rc6; + runtime_info->has_rc6p = device_info->has_rc6p; + runtime_info->ppgtt = device_info->ppgtt; + runtime_info->page_sizes = device_info->page_sizes; + runtime_info->ring_mask = device_info->ring_mask; + runtime_info->num_pipes = device_info->num_pipes; /* * Initialize GEN and platform masks. @@ -1727,7 +1727,7 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) return PTR_ERR(dev_priv); /* Disable nuclear pageflip by default on pre-ILK */ - if (!i915_modparams.nuclear_pageflip && match_info->__gen < 5) + if (!i915_modparams.nuclear_pageflip && match_info->gen < 5) dev_priv->drm.driver_features &= ~DRIVER_ATOMIC; ret = pci_enable_device(pdev); diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 4fff59249932..983f538de519 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -30,7 +30,7 @@ #include "i915_selftest.h" #define PLATFORM(x) .platform = (x) -#define GEN(x) .__gen = (x) +#define GEN(x) .gen = (x) #define GEN_DEFAULT_PIPEOFFSETS \ .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ @@ -60,16 +60,16 @@ /* Keep in gen based order, and chronological order within a gen */ #define GEN_DEFAULT_PAGE_SIZES \ - .__page_sizes = I915_GTT_PAGE_SIZE_4K + .page_sizes = I915_GTT_PAGE_SIZE_4K #define GEN2_FEATURES \ GEN(2), \ - .__num_pipes = 1, \ + .num_pipes = 1, \ .has_overlay = 1, .overlay_needs_physical = 1, \ .has_gmch_display = 1, \ .hws_needs_physical = 1, \ .unfenced_needs_alignment = 1, \ - .__ring_mask = RENDER_RING, \ + .ring_mask = RENDER_RING, \ .has_snoop = true, \ .has_coherent_ggtt = false, \ GEN_DEFAULT_PIPEOFFSETS, \ @@ -80,7 +80,7 @@ static const struct intel_device_info intel_i830_info = { GEN2_FEATURES, PLATFORM(INTEL_I830), .is_mobile = 1, .cursor_needs_physical = 1, - .__num_pipes = 2, /* legal, last one wins */ + .num_pipes = 2, /* legal, last one wins */ }; static const struct intel_device_info intel_i845g_info = { @@ -92,9 +92,9 @@ static const struct intel_device_info intel_i85x_info = { GEN2_FEATURES, PLATFORM(INTEL_I85X), .is_mobile = 1, - .__num_pipes = 2, /* legal, last one wins */ + .num_pipes = 2, /* legal, last one wins */ .cursor_needs_physical = 1, - .__has_fbc = 1, + .has_fbc = 1, }; static const struct intel_device_info intel_i865g_info = { @@ -104,9 +104,9 @@ static const struct intel_device_info intel_i865g_info = { #define GEN3_FEATURES \ GEN(3), \ - .__num_pipes = 2, \ + .num_pipes = 2, \ .has_gmch_display = 1, \ - .__ring_mask = RENDER_RING, \ + .ring_mask = RENDER_RING, \ .has_snoop = true, \ .has_coherent_ggtt = true, \ GEN_DEFAULT_PIPEOFFSETS, \ @@ -130,7 +130,7 @@ static const struct intel_device_info intel_i915gm_info = { .cursor_needs_physical = 1, .has_overlay = 1, .overlay_needs_physical = 1, .supports_tv = 1, - .__has_fbc = 1, + .has_fbc = 1, .hws_needs_physical = 1, .unfenced_needs_alignment = 1, }; @@ -151,7 +151,7 @@ static const struct intel_device_info intel_i945gm_info = { .has_hotplug = 1, .cursor_needs_physical = 1, .has_overlay = 1, .overlay_needs_physical = 1, .supports_tv = 1, - .__has_fbc = 1, + .has_fbc = 1, .hws_needs_physical = 1, .unfenced_needs_alignment = 1, }; @@ -173,10 +173,10 @@ static const struct intel_device_info intel_pineview_info = { #define GEN4_FEATURES \ GEN(4), \ - .__num_pipes = 2, \ + .num_pipes = 2, \ .has_hotplug = 1, \ .has_gmch_display = 1, \ - .__ring_mask = RENDER_RING, \ + .ring_mask = RENDER_RING, \ .has_snoop = true, \ .has_coherent_ggtt = true, \ GEN_DEFAULT_PIPEOFFSETS, \ @@ -194,7 +194,7 @@ static const struct intel_device_info intel_i965g_info = { static const struct intel_device_info intel_i965gm_info = { GEN4_FEATURES, PLATFORM(INTEL_I965GM), - .is_mobile = 1, .__has_fbc = 1, + .is_mobile = 1, .has_fbc = 1, .has_overlay = 1, .supports_tv = 1, .hws_needs_physical = 1, @@ -204,26 +204,26 @@ static const struct intel_device_info intel_i965gm_info = { static const struct intel_device_info intel_g45_info = { GEN4_FEATURES, PLATFORM(INTEL_G45), - .__ring_mask = RENDER_RING | BSD_RING, + .ring_mask = RENDER_RING | BSD_RING, }; static const struct intel_device_info intel_gm45_info = { GEN4_FEATURES, PLATFORM(INTEL_GM45), - .is_mobile = 1, .__has_fbc = 1, + .is_mobile = 1, .has_fbc = 1, .supports_tv = 1, - .__ring_mask = RENDER_RING | BSD_RING, + .ring_mask = RENDER_RING | BSD_RING, }; #define GEN5_FEATURES \ GEN(5), \ - .__num_pipes = 2, \ + .num_pipes = 2, \ .has_hotplug = 1, \ - .__ring_mask = RENDER_RING | BSD_RING, \ + .ring_mask = RENDER_RING | BSD_RING, \ .has_snoop = true, \ .has_coherent_ggtt = true, \ /* ilk does support rc6, but we do not implement [power] contexts */ \ - .__has_rc6 = 0, \ + .has_rc6 = 0, \ GEN_DEFAULT_PIPEOFFSETS, \ GEN_DEFAULT_PAGE_SIZES, \ CURSOR_OFFSETS @@ -236,20 +236,20 @@ static const struct intel_device_info intel_ironlake_d_info = { static const struct intel_device_info intel_ironlake_m_info = { GEN5_FEATURES, PLATFORM(INTEL_IRONLAKE), - .is_mobile = 1, .__has_fbc = 1, + .is_mobile = 1, .has_fbc = 1, }; #define GEN6_FEATURES \ GEN(6), \ - .__num_pipes = 2, \ + .num_pipes = 2, \ .has_hotplug = 1, \ - .__has_fbc = 1, \ - .__ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ + .has_fbc = 1, \ + .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ .has_coherent_ggtt = true, \ .has_llc = 1, \ - .__has_rc6 = 1, \ - .__has_rc6p = 1, \ - .__ppgtt = INTEL_PPGTT_ALIASING, \ + .has_rc6 = 1, \ + .has_rc6p = 1, \ + .ppgtt = INTEL_PPGTT_ALIASING, \ GEN_DEFAULT_PIPEOFFSETS, \ GEN_DEFAULT_PAGE_SIZES, \ CURSOR_OFFSETS @@ -286,15 +286,15 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = { #define GEN7_FEATURES \ GEN(7), \ - .__num_pipes = 3, \ + .num_pipes = 3, \ .has_hotplug = 1, \ - .__has_fbc = 1, \ - .__ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ + .has_fbc = 1, \ + .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ .has_coherent_ggtt = true, \ .has_llc = 1, \ - .__has_rc6 = 1, \ - .__has_rc6p = 1, \ - .__ppgtt = INTEL_PPGTT_FULL, \ + .has_rc6 = 1, \ + .has_rc6p = 1, \ + .ppgtt = INTEL_PPGTT_FULL, \ GEN_DEFAULT_PIPEOFFSETS, \ GEN_DEFAULT_PAGE_SIZES, \ IVB_CURSOR_OFFSETS @@ -334,7 +334,7 @@ static const struct intel_device_info intel_ivybridge_q_info = { GEN7_FEATURES, PLATFORM(INTEL_IVYBRIDGE), .gt = 2, - .__num_pipes = 0, /* legal, last one wins */ + .num_pipes = 0, /* legal, last one wins */ .has_l3_dpf = 1, }; @@ -342,15 +342,15 @@ static const struct intel_device_info intel_valleyview_info = { PLATFORM(INTEL_VALLEYVIEW), GEN(7), .is_lp = 1, - .__num_pipes = 2, + .num_pipes = 2, .has_runtime_pm = 1, - .__has_rc6 = 1, + .has_rc6 = 1, .has_gmch_display = 1, .has_hotplug = 1, - .__ppgtt = INTEL_PPGTT_FULL, + .ppgtt = INTEL_PPGTT_FULL, .has_snoop = true, .has_coherent_ggtt = false, - .__ring_mask = RENDER_RING | BSD_RING | BLT_RING, + .ring_mask = RENDER_RING | BSD_RING | BLT_RING, .display_mmio_offset = VLV_DISPLAY_BASE, GEN_DEFAULT_PAGE_SIZES, GEN_DEFAULT_PIPEOFFSETS, @@ -359,12 +359,12 @@ static const struct intel_device_info intel_valleyview_info = { #define G75_FEATURES \ GEN7_FEATURES, \ - .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ .has_ddi = 1, \ .has_fpga_dbg = 1, \ .has_psr = 1, \ .has_dp_mst = 1, \ - .__has_rc6p = 0 /* RC6p removed-by HSW */, \ + .has_rc6p = 0 /* RC6p removed-by HSW */, \ .has_runtime_pm = 1 #define HSW_PLATFORM \ @@ -391,10 +391,10 @@ static const struct intel_device_info intel_haswell_gt3_info = { G75_FEATURES, \ GEN(8), \ BDW_COLORS, \ - .__page_sizes = I915_GTT_PAGE_SIZE_4K | \ + .page_sizes = I915_GTT_PAGE_SIZE_4K | \ I915_GTT_PAGE_SIZE_2M, \ .has_logical_ring_contexts = 1, \ - .__ppgtt = INTEL_PPGTT_FULL_4LVL, \ + .ppgtt = INTEL_PPGTT_FULL_4LVL, \ .has_64bit_reloc = 1, \ .has_reset_engine = 1 @@ -423,22 +423,22 @@ static const struct intel_device_info intel_broadwell_rsvd_info = { static const struct intel_device_info intel_broadwell_gt3_info = { BDW_PLATFORM, .gt = 3, - .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, }; static const struct intel_device_info intel_cherryview_info = { PLATFORM(INTEL_CHERRYVIEW), GEN(8), - .__num_pipes = 3, + .num_pipes = 3, .has_hotplug = 1, .is_lp = 1, - .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, .has_64bit_reloc = 1, .has_runtime_pm = 1, - .__has_rc6 = 1, + .has_rc6 = 1, .has_logical_ring_contexts = 1, .has_gmch_display = 1, - .__ppgtt = INTEL_PPGTT_FULL, + .ppgtt = INTEL_PPGTT_FULL, .has_reset_engine = 1, .has_snoop = true, .has_coherent_ggtt = false, @@ -450,7 +450,7 @@ static const struct intel_device_info intel_cherryview_info = { }; #define GEN9_DEFAULT_PAGE_SIZES \ - .__page_sizes = I915_GTT_PAGE_SIZE_4K | \ + .page_sizes = I915_GTT_PAGE_SIZE_4K | \ I915_GTT_PAGE_SIZE_64K | \ I915_GTT_PAGE_SIZE_2M @@ -482,7 +482,7 @@ static const struct intel_device_info intel_skylake_gt2_info = { #define SKL_GT3_PLUS_PLATFORM \ SKL_PLATFORM, \ - .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING static const struct intel_device_info intel_skylake_gt3_info = { @@ -499,21 +499,21 @@ static const struct intel_device_info intel_skylake_gt4_info = { GEN(9), \ .is_lp = 1, \ .has_hotplug = 1, \ - .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ - .__num_pipes = 3, \ + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ + .num_pipes = 3, \ .has_64bit_reloc = 1, \ .has_ddi = 1, \ .has_fpga_dbg = 1, \ - .__has_fbc = 1, \ + .has_fbc = 1, \ .has_psr = 1, \ .has_runtime_pm = 1, \ .has_csr = 1, \ - .__has_rc6 = 1, \ + .has_rc6 = 1, \ .has_dp_mst = 1, \ .has_logical_ring_contexts = 1, \ .has_logical_ring_preemption = 1, \ .has_guc = 1, \ - .__ppgtt = INTEL_PPGTT_FULL_4LVL, \ + .ppgtt = INTEL_PPGTT_FULL_4LVL, \ .has_reset_engine = 1, \ .has_snoop = true, \ .has_coherent_ggtt = false, \ @@ -553,7 +553,7 @@ static const struct intel_device_info intel_kabylake_gt2_info = { static const struct intel_device_info intel_kabylake_gt3_info = { KBL_PLATFORM, .gt = 3, - .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, }; #define CFL_PLATFORM \ @@ -573,7 +573,7 @@ static const struct intel_device_info intel_coffeelake_gt2_info = { static const struct intel_device_info intel_coffeelake_gt3_info = { CFL_PLATFORM, .gt = 3, - .__ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, + .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, }; #define GEN10_FEATURES \ @@ -605,7 +605,7 @@ static const struct intel_device_info intel_icelake_11_info = { GEN11_FEATURES, PLATFORM(INTEL_ICELAKE), .is_alpha_support = 1, - .__ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING, + .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING, }; #undef GEN diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index b9d08428f35b..6c2f6bec6156 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -130,7 +130,7 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv, INTEL_DEVID(dev_priv), INTEL_REVID(dev_priv), intel_platform_name(INTEL_INFO(dev_priv)->platform), - INTEL_INFO(dev_priv)->__gen); + INTEL_GEN(dev_priv)); intel_device_info_dump_flags(INTEL_INFO(dev_priv), p); } diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 91f163039949..8060a2713bac 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -93,7 +93,7 @@ enum intel_ppgtt { func(has_ddi); \ func(has_dp_mst); \ func(has_reset_engine); \ - func(__has_fbc); \ + func(has_fbc); \ func(has_fpga_dbg); \ func(has_gmch_display); \ func(has_guc); \ @@ -106,8 +106,8 @@ enum intel_ppgtt { func(has_logical_ring_preemption); \ func(has_overlay); \ func(has_psr); \ - func(__has_rc6); \ - func(__has_rc6p); \ + func(has_rc6); \ + func(has_rc6p); \ func(has_runtime_pm); \ func(has_snoop); \ func(has_coherent_ggtt); \ @@ -148,15 +148,15 @@ struct sseu_dev_info { typedef u8 intel_ring_mask_t; struct intel_device_info { - u8 __gen; + u8 gen; u8 gt; /* GT number, 0 if undefined */ - intel_ring_mask_t __ring_mask; /* Rings supported by the HW */ - u8 __num_pipes; + intel_ring_mask_t ring_mask; /* Rings supported by the HW */ + u8 num_pipes; enum intel_platform platform; - enum intel_ppgtt __ppgtt; - unsigned int __page_sizes; /* page sizes supported by the HW */ + enum intel_ppgtt ppgtt; + unsigned int page_sizes; /* page sizes supported by the HW */ u32 display_mmio_offset;