From patchwork Fri Nov 16 12:07:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 10686131 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 10ED21709 for ; Fri, 16 Nov 2018 12:07:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F1F9A287FF for ; Fri, 16 Nov 2018 12:07:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E4E4E2CB7B; Fri, 16 Nov 2018 12:07:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 66844287FF for ; Fri, 16 Nov 2018 12:07:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A49676E6D5; Fri, 16 Nov 2018 12:07:02 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 920866E6D5 for ; Fri, 16 Nov 2018 12:06:59 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Nov 2018 04:06:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,240,1539673200"; d="scan'208";a="108680494" Received: from jnikula-mobl3.fi.intel.com (HELO localhost) ([10.237.72.61]) by fmsmga001.fm.intel.com with ESMTP; 16 Nov 2018 04:06:58 -0800 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Nov 2018 14:07:26 +0200 Message-Id: <20181116120729.7580-2-jani.nikula@intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181116120729.7580-1-jani.nikula@intel.com> References: <20181116120729.7580-1-jani.nikula@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH v2 2/5] drm/i915/fixed: prefer kernel types over stdint types X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP While at it, conform to kernel spacing (i.e. no space) after cast. No functional changes. Reviewed-by: Joonas Lahtinen Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_fixed.h | 61 +++++++++++++++++++-------------------- 1 file changed, 29 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_fixed.h b/drivers/gpu/drm/i915/i915_fixed.h index c974e51c6d8b..6c914940b4a9 100644 --- a/drivers/gpu/drm/i915/i915_fixed.h +++ b/drivers/gpu/drm/i915/i915_fixed.h @@ -7,7 +7,7 @@ #define _I915_FIXED_H_ typedef struct { - uint32_t val; + u32 val; } uint_fixed_16_16_t; #define FP_16_16_MAX ({ \ @@ -23,7 +23,7 @@ static inline bool is_fixed16_zero(uint_fixed_16_16_t val) return false; } -static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val) +static inline uint_fixed_16_16_t u32_to_fixed16(u32 val) { uint_fixed_16_16_t fp; @@ -33,12 +33,12 @@ static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val) return fp; } -static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp) +static inline u32 fixed16_to_u32_round_up(uint_fixed_16_16_t fp) { return DIV_ROUND_UP(fp.val, 1 << 16); } -static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp) +static inline u32 fixed16_to_u32(uint_fixed_16_16_t fp) { return fp.val >> 16; } @@ -61,86 +61,83 @@ static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1, return max; } -static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val) +static inline uint_fixed_16_16_t clamp_u64_to_fixed16(u64 val) { uint_fixed_16_16_t fp; WARN_ON(val > U32_MAX); - fp.val = (uint32_t) val; + fp.val = (u32)val; return fp; } -static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val, - uint_fixed_16_16_t d) +static inline u32 div_round_up_fixed16(uint_fixed_16_16_t val, + uint_fixed_16_16_t d) { return DIV_ROUND_UP(val.val, d.val); } -static inline uint32_t mul_round_up_u32_fixed16(uint32_t val, - uint_fixed_16_16_t mul) +static inline u32 mul_round_up_u32_fixed16(u32 val, uint_fixed_16_16_t mul) { - uint64_t intermediate_val; + u64 intermediate_val; - intermediate_val = (uint64_t) val * mul.val; + intermediate_val = (u64)val * mul.val; intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16); WARN_ON(intermediate_val > U32_MAX); - return (uint32_t) intermediate_val; + return (u32)intermediate_val; } static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val, uint_fixed_16_16_t mul) { - uint64_t intermediate_val; + u64 intermediate_val; - intermediate_val = (uint64_t) val.val * mul.val; + intermediate_val = (u64)val.val * mul.val; intermediate_val = intermediate_val >> 16; return clamp_u64_to_fixed16(intermediate_val); } -static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d) +static inline uint_fixed_16_16_t div_fixed16(u32 val, u32 d) { - uint64_t interm_val; + u64 interm_val; - interm_val = (uint64_t)val << 16; + interm_val = (u64)val << 16; interm_val = DIV_ROUND_UP_ULL(interm_val, d); return clamp_u64_to_fixed16(interm_val); } -static inline uint32_t div_round_up_u32_fixed16(uint32_t val, - uint_fixed_16_16_t d) +static inline u32 div_round_up_u32_fixed16(u32 val, uint_fixed_16_16_t d) { - uint64_t interm_val; + u64 interm_val; - interm_val = (uint64_t)val << 16; + interm_val = (u64)val << 16; interm_val = DIV_ROUND_UP_ULL(interm_val, d.val); WARN_ON(interm_val > U32_MAX); - return (uint32_t) interm_val; + return (u32)interm_val; } -static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val, - uint_fixed_16_16_t mul) +static inline uint_fixed_16_16_t mul_u32_fixed16(u32 val, uint_fixed_16_16_t mul) { - uint64_t intermediate_val; + u64 intermediate_val; - intermediate_val = (uint64_t) val * mul.val; + intermediate_val = (u64)val * mul.val; return clamp_u64_to_fixed16(intermediate_val); } static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1, uint_fixed_16_16_t add2) { - uint64_t interm_sum; + u64 interm_sum; - interm_sum = (uint64_t) add1.val + add2.val; + interm_sum = (u64)add1.val + add2.val; return clamp_u64_to_fixed16(interm_sum); } static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1, - uint32_t add2) + u32 add2) { - uint64_t interm_sum; + u64 interm_sum; uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2); - interm_sum = (uint64_t) add1.val + interm_add2.val; + interm_sum = (u64)add1.val + interm_add2.val; return clamp_u64_to_fixed16(interm_sum); }