diff mbox series

[2/2] drm/i915/dp: Fix inconsistent indenting

Message ID 20181120202439.13017-2-chris@chris-wilson.co.uk (mailing list archive)
State New, archived
Headers show
Series [1/2] drm/i915/gvt: Avoid use-after-free iterating the gtt list | expand

Commit Message

Chris Wilson Nov. 20, 2018, 8:24 p.m. UTC
Always show the FEC capability as it is initialised to 0 before error.
Fixing,

drivers/gpu/drm/i915/intel_dp.c:3846 intel_dp_get_dsc_sink_cap() warn: inconsistent indenting

Fixes: 08cadae8e157 ("i915/dp/fec: Cache the FEC_CAPABLE DPCD register")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

Comments

Srivatsa, Anusha Dec. 3, 2018, 10:43 p.m. UTC | #1
>-----Original Message-----
>From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
>Sent: Tuesday, November 20, 2018 12:25 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Chris Wilson <chris@chris-wilson.co.uk>; Jani Nikula
><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>;
>Navare, Manasi D <manasi.d.navare@intel.com>; Srivatsa, Anusha
><anusha.srivatsa@intel.com>
>Subject: [PATCH 2/2] drm/i915/dp: Fix inconsistent indenting
>
>Always show the FEC capability as it is initialised to 0 before error.
>Fixing,
>
>drivers/gpu/drm/i915/intel_dp.c:3846 intel_dp_get_dsc_sink_cap() warn:
>inconsistent indenting
>
>Fixes: 08cadae8e157 ("i915/dp/fec: Cache the FEC_CAPABLE DPCD register")
>Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>Cc: Jani Nikula <jani.nikula@linux.intel.com>
>Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>Cc: Manasi Navare <manasi.d.navare@intel.com>
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>

Thanks for the fix and the above mentioned changes. Looks good.

Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>

>---
> drivers/gpu/drm/i915/intel_dp.c | 13 ++++++-------
> 1 file changed, 6 insertions(+), 7 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>index 7699f9b7b2d2..de6c982b1d1e 100644
>--- a/drivers/gpu/drm/i915/intel_dp.c
>+++ b/drivers/gpu/drm/i915/intel_dp.c
>@@ -3837,15 +3837,14 @@ static void intel_dp_get_dsc_sink_cap(struct
>intel_dp *intel_dp)
> 		DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
> 			      (int)sizeof(intel_dp->dsc_dpcd),
> 			      intel_dp->dsc_dpcd);
>+
> 		/* FEC is supported only on DP 1.4 */
>-		if (!intel_dp_is_edp(intel_dp)) {
>-			if (drm_dp_dpcd_readb(&intel_dp->aux,
>DP_FEC_CAPABILITY,
>-					      &intel_dp->fec_capable) < 0)
>-				DRM_ERROR("Failed to read FEC DPCD
>register\n");
>+		if (!intel_dp_is_edp(intel_dp) &&
>+		    drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
>+				      &intel_dp->fec_capable) < 0)
>+			DRM_ERROR("Failed to read FEC DPCD register\n");
>
>-		DRM_DEBUG_KMS("FEC CAPABILITY: %x\n",
>-			      intel_dp->fec_capable);
>-		}
>+		DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp-
>>fec_capable);
> 	}
> }
>
>--
>2.19.1
Navare, Manasi Dec. 3, 2018, 10:55 p.m. UTC | #2
On Tue, Nov 20, 2018 at 08:24:39PM +0000, Chris Wilson wrote:
> Always show the FEC capability as it is initialised to 0 before error.

That is a good point, do you think we should do the same for DSC DPCD and print
that unconditionally?

Manasi

> Fixing,
> 
> drivers/gpu/drm/i915/intel_dp.c:3846 intel_dp_get_dsc_sink_cap() warn: inconsistent indenting
> 
> Fixes: 08cadae8e157 ("i915/dp/fec: Cache the FEC_CAPABLE DPCD register")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 13 ++++++-------
>  1 file changed, 6 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 7699f9b7b2d2..de6c982b1d1e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3837,15 +3837,14 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
>  		DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
>  			      (int)sizeof(intel_dp->dsc_dpcd),
>  			      intel_dp->dsc_dpcd);
> +
>  		/* FEC is supported only on DP 1.4 */
> -		if (!intel_dp_is_edp(intel_dp)) {
> -			if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
> -					      &intel_dp->fec_capable) < 0)
> -				DRM_ERROR("Failed to read FEC DPCD register\n");
> +		if (!intel_dp_is_edp(intel_dp) &&
> +		    drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
> +				      &intel_dp->fec_capable) < 0)
> +			DRM_ERROR("Failed to read FEC DPCD register\n");
>  
> -		DRM_DEBUG_KMS("FEC CAPABILITY: %x\n",
> -			      intel_dp->fec_capable);
> -		}
> +		DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
>  	}
>  }
>  
> -- 
> 2.19.1
>
Chris Wilson Dec. 4, 2018, 9:31 a.m. UTC | #3
Quoting Manasi Navare (2018-12-03 22:55:16)
> On Tue, Nov 20, 2018 at 08:24:39PM +0000, Chris Wilson wrote:
> > Always show the FEC capability as it is initialised to 0 before error.
> 
> That is a good point, do you think we should do the same for DSC DPCD and print
> that unconditionally?

Yes, when looking for debug prints I don't always remember under what
conditions they don't get printed. So for something like link
capabilities explicitly telling me some feature is not present is more
foolproof.

It's your call though, you need to balance debug output so that you get
the information you need without too large of a haystack. :)
-Chris
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7699f9b7b2d2..de6c982b1d1e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3837,15 +3837,14 @@  static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
 		DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
 			      (int)sizeof(intel_dp->dsc_dpcd),
 			      intel_dp->dsc_dpcd);
+
 		/* FEC is supported only on DP 1.4 */
-		if (!intel_dp_is_edp(intel_dp)) {
-			if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
-					      &intel_dp->fec_capable) < 0)
-				DRM_ERROR("Failed to read FEC DPCD register\n");
+		if (!intel_dp_is_edp(intel_dp) &&
+		    drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
+				      &intel_dp->fec_capable) < 0)
+			DRM_ERROR("Failed to read FEC DPCD register\n");
 
-		DRM_DEBUG_KMS("FEC CAPABILITY: %x\n",
-			      intel_dp->fec_capable);
-		}
+		DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
 	}
 }