From patchwork Thu Dec 6 00:05:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 10715151 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4907717D5 for ; Thu, 6 Dec 2018 00:04:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 399D22D6F7 for ; Thu, 6 Dec 2018 00:04:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2D7D12D9C5; Thu, 6 Dec 2018 00:04:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BB5892D6F7 for ; Thu, 6 Dec 2018 00:04:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DB5D06E502; Thu, 6 Dec 2018 00:04:28 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 160956E502 for ; Thu, 6 Dec 2018 00:04:27 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Dec 2018 16:04:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,320,1539673200"; d="scan'208";a="301399695" Received: from invictus.jf.intel.com ([10.54.75.159]) by fmsmga005.fm.intel.com with ESMTP; 05 Dec 2018 16:04:21 -0800 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Dec 2018 16:05:00 -0800 Message-Id: <20181206000500.3297-1-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.17.1 Subject: [Intel-gfx] [PATCH v3] drm/i915/cnl: Fix the formulae for register offsets X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rodrigo Vivi , Lucs De Marchi MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP For gen10+ the offsets for Slice PG cntl/ EU PG cntl donot scale well for higher slices. v2: Use _PICK instead of formulae(Jani) v3: Remove superfluous newlines(Jani) Cc: Rodrigo Vivi Cc: Lucs De Marchi Cc: Daniele Ceraolo Spurio Reviewed-by: Jani Nikula Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/i915_reg.h | 51 +++++++++++++++++++++++++++++---- 1 file changed, 45 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0a7d60509ca7..a7f9f8da8e88 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8675,18 +8675,57 @@ enum { #define CHV_EU311_PG_ENABLE (1 << 1) #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4) -#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ - ((slice) % 3) * 0x4) + +#define _CNL_SLICE0_PGCTL_ACK 0x804c +#define _CNL_SLICE1_PGCTL_ACK 0x8050 +#define _CNL_SLICE2_PGCTL_ACK 0x8054 +#define _CNL_SLICE3_PGCTL_ACK 0x8080 +#define _CNL_SLICE4_PGCTL_ACK 0x8084 +#define _CNL_SLICE5_PGCTL_ACK 0x8088 +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(_PICK(slice, \ + _CNL_SLICE0_PGCTL_ACK, \ + _CNL_SLICE1_PGCTL_ACK, \ + _CNL_SLICE2_PGCTL_ACK, \ + _CNL_SLICE3_PGCTL_ACK, \ + _CNL_SLICE4_PGCTL_ACK, \ + _CNL_SLICE5_PGCTL_ACK)) + #define GEN9_PGCTL_SLICE_ACK (1 << 0) #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2)) #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F) #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8) -#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ - ((slice) % 3) * 0x8) + +#define _CNL_SLICE0_SS01_EU_PGCTL_ACK 0x805c +#define _CNL_SLICE1_SS01_EU_PGCTL_ACK 0x8064 +#define _CNL_SLICE2_SS01_EU_PGCTL_ACK 0x806c +#define _CNL_SLICE3_SS01_EU_PGCTL_ACK 0x808c +#define _CNL_SLICE4_SS01_EU_PGCTL_ACK 0x8094 +#define _CNL_SLICE5_SS01_EU_PGCTL_ACK 0x809c +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(_PICK(slice, \ + _CNL_SLICE0_SS01_EU_PGCTL_ACK, \ + _CNL_SLICE1_SS01_EU_PGCTL_ACK, \ + _CNL_SLICE2_SS01_EU_PGCTL_ACK, \ + _CNL_SLICE3_SS01_EU_PGCTL_ACK, \ + _CNL_SLICE4_SS01_EU_PGCTL_ACK, \ + _CNL_SLICE5_SS01_EU_PGCTL_ACK)) + #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8) -#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \ - ((slice) % 3) * 0x8) + +#define _CNL_SLICE0_SS23_EU_PGCTL_ACK 0x8060 +#define _CNL_SLICE1_SS23_EU_PGCTL_ACK 0x8068 +#define _CNL_SLICE2_SS23_EU_PGCTL_ACK 0x8070 +#define _CNL_SLICE3_SS23_EU_PGCTL_ACK 0x8090 +#define _CNL_SLICE4_SS23_EU_PGCTL_ACK 0x8098 +#define _CNL_SLICE5_SS23_EU_PGCTL_ACK 0x80a0 +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(_PICK(slice, \ + _CNL_SLICE0_SS23_EU_PGCTL_ACK, \ + _CNL_SLICE1_SS23_EU_PGCTL_ACK, \ + _CNL_SLICE2_SS23_EU_PGCTL_ACK, \ + _CNL_SLICE3_SS23_EU_PGCTL_ACK, \ + _CNL_SLICE4_SS23_EU_PGCTL_ACK, \ + _CNL_SLICE5_SS23_EU_PGCTL_ACK)) + #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)