From patchwork Wed Dec 12 19:38:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 10726981 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A4C5591E for ; Wed, 12 Dec 2018 19:38:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 95E902B86C for ; Wed, 12 Dec 2018 19:38:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8A5222B87F; Wed, 12 Dec 2018 19:38:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A171A2B86C for ; Wed, 12 Dec 2018 19:38:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E36776EB6F; Wed, 12 Dec 2018 19:38:31 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id B96A56EB6F for ; Wed, 12 Dec 2018 19:38:30 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Dec 2018 11:38:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,345,1539673200"; d="scan'208";a="117842025" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga002.jf.intel.com with SMTP; 12 Dec 2018 11:38:27 -0800 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Dec 2018 21:38:27 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 12 Dec 2018 21:38:20 +0200 Message-Id: <20181212193824.3017-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20181212193824.3017-1-ville.syrjala@linux.intel.com> References: <20181212193824.3017-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/6] drm/i915: Rename ilk watermark structs/enums X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä Rename all the watermark related structs/enums specific to ilk-bdw to have an ilk_ prefix rather than an intel_ prefix. Should make it less confusing for everyone when it's clear where these things get used. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h | 12 ++-- drivers/gpu/drm/i915/intel_drv.h | 10 ++-- drivers/gpu/drm/i915/intel_pm.c | 96 ++++++++++++++++---------------- 3 files changed, 58 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9264fd1b8662..95231f5f813d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1024,12 +1024,12 @@ struct intel_vbt_data { struct sdvo_device_mapping sdvo_mappings[2]; }; -enum intel_ddb_partitioning { - INTEL_DDB_PART_1_2, - INTEL_DDB_PART_5_6, /* IVB+ */ +enum ilk_ddb_partitioning { + ILK_DDB_PART_1_2, + ILK_DDB_PART_5_6, /* IVB+ */ }; -struct intel_wm_level { +struct ilk_wm_level { bool enable; u16 pri_val; u16 spr_val; @@ -1043,7 +1043,7 @@ struct ilk_wm_values { u32 wm_lp_spr[3]; u32 wm_linetime[3]; bool enable_fbc_wm; - enum intel_ddb_partitioning partitioning; + enum ilk_ddb_partitioning partitioning; }; struct g4x_pipe_wm { @@ -1195,7 +1195,7 @@ struct i915_virtual_gpu { }; /* used in computing the new watermarks state */ -struct intel_wm_config { +struct ilk_wm_config { unsigned int num_pipes_active; bool sprites_enabled; bool sprites_scaled; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 09abc1035335..cc4d8d8382b6 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -628,8 +628,8 @@ struct intel_crtc_scaler_state { /* Flag to get scanline using frame time stamps */ #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1) -struct intel_pipe_wm { - struct intel_wm_level wm[5]; +struct ilk_pipe_wm { + struct ilk_wm_level wm[5]; u32 linetime; bool fbc_wm_enabled; bool pipe_enabled; @@ -693,13 +693,13 @@ struct intel_crtc_wm_state { * switching away from and the new * configuration we're switching to. */ - struct intel_pipe_wm intermediate; + struct ilk_pipe_wm intermediate; /* * Optimal watermarks, programmed post-vblank * when this state is committed. */ - struct intel_pipe_wm optimal; + struct ilk_pipe_wm optimal; } ilk; struct { @@ -982,7 +982,7 @@ struct intel_crtc { struct { /* watermarks currently being used */ union { - struct intel_pipe_wm ilk; + struct ilk_pipe_wm ilk; struct vlv_wm_state vlv; struct g4x_wm_state g4x; } active; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f23ea4631f9b..6328f0f8aa88 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2485,8 +2485,7 @@ struct ilk_wm_maximums { */ static u16 ilk_compute_pri_wm(const struct intel_crtc_state *cstate, const struct intel_plane_state *pstate, - unsigned int mem_value, - bool is_lp) + unsigned int mem_value, bool is_lp) { u16 method1, method2; int cpp; @@ -2623,8 +2622,8 @@ static u16 ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv) /* Calculate the maximum primary/sprite plane watermark */ static u16 ilk_plane_wm_max(const struct drm_i915_private *dev_priv, int level, - const struct intel_wm_config *config, - enum intel_ddb_partitioning ddb_partitioning, + const struct ilk_wm_config *config, + enum ilk_ddb_partitioning ddb_partitioning, bool is_sprite) { u16 fifo_size = ilk_display_fifo_size(dev_priv); @@ -2648,7 +2647,7 @@ static u16 ilk_plane_wm_max(const struct drm_i915_private *dev_priv, if (config->sprites_enabled) { /* level 0 is always calculated with 1:1 split */ - if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { + if (level > 0 && ddb_partitioning == ILK_DDB_PART_5_6) { if (is_sprite) fifo_size *= 5; fifo_size /= 6; @@ -2664,7 +2663,7 @@ static u16 ilk_plane_wm_max(const struct drm_i915_private *dev_priv, /* Calculate the maximum cursor plane watermark */ static u16 ilk_cursor_wm_max(const struct drm_i915_private *dev_priv, int level, - const struct intel_wm_config *config) + const struct ilk_wm_config *config) { /* HSW LP1+ watermarks w/ multiple pipes */ if (level > 0 && config->num_pipes_active > 1) @@ -2676,8 +2675,8 @@ static u16 ilk_cursor_wm_max(const struct drm_i915_private *dev_priv, static void ilk_compute_wm_maximums(const struct drm_i915_private *dev_priv, int level, - const struct intel_wm_config *config, - enum intel_ddb_partitioning ddb_partitioning, + const struct ilk_wm_config *config, + enum ilk_ddb_partitioning ddb_partitioning, struct ilk_wm_maximums *max) { max->pri = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, false); @@ -2698,7 +2697,7 @@ static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv, static bool ilk_validate_wm_level(int level, const struct ilk_wm_maximums *max, - struct intel_wm_level *result) + struct ilk_wm_level *result) { bool ret; @@ -2744,7 +2743,7 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, const struct intel_plane_state *pristate, const struct intel_plane_state *sprstate, const struct intel_plane_state *curstate, - struct intel_wm_level *result) + struct ilk_wm_level *result) { u16 pri_latency = dev_priv->wm.pri_latency[level]; u16 spr_latency = dev_priv->wm.spr_latency[level]; @@ -3068,10 +3067,10 @@ static void skl_setup_wm_latency(struct drm_i915_private *dev_priv) } static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv, - struct intel_pipe_wm *pipe_wm) + struct ilk_pipe_wm *pipe_wm) { /* LP0 watermark maximums depend on this pipe alone */ - const struct intel_wm_config config = { + const struct ilk_wm_config config = { .num_pipes_active = 1, .sprites_enabled = pipe_wm->sprites_enabled, .sprites_scaled = pipe_wm->sprites_scaled, @@ -3079,7 +3078,7 @@ static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv, struct ilk_wm_maximums max; /* LP0 watermarks always use 1/2 DDB partitioning */ - ilk_compute_wm_maximums(dev_priv, 0, &config, INTEL_DDB_PART_1_2, &max); + ilk_compute_wm_maximums(dev_priv, 0, &config, ILK_DDB_PART_1_2, &max); /* At least LP0 must be valid */ if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) { @@ -3095,7 +3094,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate) { struct drm_atomic_state *state = cstate->base.state; struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); - struct intel_pipe_wm *pipe_wm; + struct ilk_pipe_wm *pipe_wm; struct drm_device *dev = state->dev; const struct drm_i915_private *dev_priv = to_i915(dev); struct drm_plane *plane; @@ -3150,7 +3149,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate) ilk_compute_wm_reg_maximums(dev_priv, 1, &max); for (level = 1; level <= usable_level; level++) { - struct intel_wm_level *wm = &pipe_wm->wm[level]; + struct ilk_wm_level *wm = &pipe_wm->wm[level]; ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, pristate, sprstate, curstate, wm); @@ -3178,12 +3177,12 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate) { struct intel_crtc *intel_crtc = to_intel_crtc(newstate->base.crtc); struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); - struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate; + struct ilk_pipe_wm *a = &newstate->wm.ilk.intermediate; struct intel_atomic_state *intel_state = to_intel_atomic_state(newstate->base.state); const struct intel_crtc_state *oldstate = intel_atomic_get_old_crtc_state(intel_state, intel_crtc); - const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal; + const struct ilk_pipe_wm *b = &oldstate->wm.ilk.optimal; int level, max_level = ilk_wm_max_level(dev_priv); /* @@ -3201,8 +3200,8 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate) a->sprites_scaled |= b->sprites_scaled; for (level = 0; level <= max_level; level++) { - struct intel_wm_level *a_wm = &a->wm[level]; - const struct intel_wm_level *b_wm = &b->wm[level]; + struct ilk_wm_level *a_wm = &a->wm[level]; + const struct ilk_wm_level *b_wm = &b->wm[level]; a_wm->enable &= b_wm->enable; a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val); @@ -3235,15 +3234,15 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate) */ static void ilk_merge_wm_level(struct drm_i915_private *dev_priv, int level, - struct intel_wm_level *ret_wm) + struct ilk_wm_level *ret_wm) { const struct intel_crtc *intel_crtc; ret_wm->enable = true; for_each_intel_crtc(&dev_priv->drm, intel_crtc) { - const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk; - const struct intel_wm_level *wm = &active->wm[level]; + const struct ilk_pipe_wm *active = &intel_crtc->wm.active.ilk; + const struct ilk_wm_level *wm = &active->wm[level]; if (!active->pipe_enabled) continue; @@ -3267,9 +3266,9 @@ static void ilk_merge_wm_level(struct drm_i915_private *dev_priv, * Merge all low power watermarks for all active pipes. */ static void ilk_wm_merge(struct drm_i915_private *dev_priv, - const struct intel_wm_config *config, + const struct ilk_wm_config *config, const struct ilk_wm_maximums *max, - struct intel_pipe_wm *merged) + struct ilk_pipe_wm *merged) { int level, max_level = ilk_wm_max_level(dev_priv); int last_enabled_level = max_level; @@ -3284,7 +3283,7 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv, /* merge each WM1+ level */ for (level = 1; level <= max_level; level++) { - struct intel_wm_level *wm = &merged->wm[level]; + struct ilk_wm_level *wm = &merged->wm[level]; ilk_merge_wm_level(dev_priv, level, wm); @@ -3314,14 +3313,14 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv, if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled && intel_fbc_is_active(dev_priv)) { for (level = 2; level <= max_level; level++) { - struct intel_wm_level *wm = &merged->wm[level]; + struct ilk_wm_level *wm = &merged->wm[level]; wm->enable = false; } } } -static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) +static int ilk_wm_lp_to_level(int wm_lp, const struct ilk_pipe_wm *pipe_wm) { /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); @@ -3338,8 +3337,8 @@ static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv, } static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, - const struct intel_pipe_wm *merged, - enum intel_ddb_partitioning partitioning, + const struct ilk_pipe_wm *merged, + enum ilk_ddb_partitioning partitioning, struct ilk_wm_values *results) { struct intel_crtc *intel_crtc; @@ -3350,7 +3349,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, /* LP1+ register values */ for (wm_lp = 1; wm_lp <= 3; wm_lp++) { - const struct intel_wm_level *r; + const struct ilk_wm_level *r; level = ilk_wm_lp_to_level(wm_lp, merged); @@ -3389,7 +3388,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, /* LP0 register values */ for_each_intel_crtc(&dev_priv->drm, intel_crtc) { enum pipe pipe = intel_crtc->pipe; - const struct intel_wm_level *r = + const struct ilk_wm_level *r = &intel_crtc->wm.active.ilk.wm[0]; if (WARN_ON(!r->enable)) @@ -3406,10 +3405,10 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, /* Find the result with the highest level enabled. Check for enable_fbc_wm in * case both are at the same level. Prefer r1 in case they're the same. */ -static struct intel_pipe_wm * +static struct ilk_pipe_wm * ilk_find_best_result(struct drm_i915_private *dev_priv, - struct intel_pipe_wm *r1, - struct intel_pipe_wm *r2) + struct ilk_pipe_wm *r1, + struct ilk_pipe_wm *r2) { int level, max_level = ilk_wm_max_level(dev_priv); int level1 = 0, level2 = 0; @@ -3557,14 +3556,14 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv, if (dirty & WM_DIRTY_DDB) { if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { val = I915_READ(WM_MISC); - if (results->partitioning == INTEL_DDB_PART_1_2) + if (results->partitioning == ILK_DDB_PART_1_2) val &= ~WM_MISC_DATA_PARTITION_5_6; else val |= WM_MISC_DATA_PARTITION_5_6; I915_WRITE(WM_MISC, val); } else { val = I915_READ(DISP_ARB_CTL2); - if (results->partitioning == INTEL_DDB_PART_1_2) + if (results->partitioning == ILK_DDB_PART_1_2) val &= ~DISP_DATA_PARTITION_5_6; else val |= DISP_DATA_PARTITION_5_6; @@ -5482,13 +5481,13 @@ static void skl_initial_wm(struct intel_atomic_state *state, } static void ilk_compute_wm_config(struct drm_i915_private *dev_priv, - struct intel_wm_config *config) + struct ilk_wm_config *config) { struct intel_crtc *crtc; /* Compute the currently _active_ config */ for_each_intel_crtc(&dev_priv->drm, crtc) { - const struct intel_pipe_wm *wm = &crtc->wm.active.ilk; + const struct ilk_pipe_wm *wm = &crtc->wm.active.ilk; if (!wm->pipe_enabled) continue; @@ -5501,21 +5500,21 @@ static void ilk_compute_wm_config(struct drm_i915_private *dev_priv, static void ilk_program_watermarks(struct drm_i915_private *dev_priv) { - struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; + struct ilk_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; struct ilk_wm_maximums max; - struct intel_wm_config config = {}; + struct ilk_wm_config config = {}; struct ilk_wm_values results = {}; - enum intel_ddb_partitioning partitioning; + enum ilk_ddb_partitioning partitioning; ilk_compute_wm_config(dev_priv, &config); - ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_1_2, &max); + ilk_compute_wm_maximums(dev_priv, 1, &config, ILK_DDB_PART_1_2, &max); ilk_wm_merge(dev_priv, &config, &max, &lp_wm_1_2); /* 5/6 split only in single pipe config on IVB+ */ if (INTEL_GEN(dev_priv) >= 7 && config.num_pipes_active == 1 && config.sprites_enabled) { - ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_5_6, &max); + ilk_compute_wm_maximums(dev_priv, 1, &config, ILK_DDB_PART_5_6, &max); ilk_wm_merge(dev_priv, &config, &max, &lp_wm_5_6); best_lp_wm = ilk_find_best_result(dev_priv, &lp_wm_1_2, &lp_wm_5_6); @@ -5524,7 +5523,7 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv) } partitioning = (best_lp_wm == &lp_wm_1_2) ? - INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; + ILK_DDB_PART_1_2 : ILK_DDB_PART_5_6; ilk_compute_wm_results(dev_priv, best_lp_wm, partitioning, &results); @@ -5628,11 +5627,10 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv) static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct ilk_wm_values *hw = &dev_priv->wm.hw; struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->base.state); - struct intel_pipe_wm *active = &cstate->wm.ilk.optimal; + struct ilk_pipe_wm *active = &cstate->wm.ilk.optimal; enum pipe pipe = crtc->pipe; static const i915_reg_t wm0_pipe_reg[] = { [PIPE_A] = WM0_PIPEA_ILK, @@ -6108,10 +6106,10 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv) if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? - INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; + ILK_DDB_PART_5_6 : ILK_DDB_PART_1_2; else if (IS_IVYBRIDGE(dev_priv)) hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? - INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; + ILK_DDB_PART_5_6 : ILK_DDB_PART_1_2; hw->enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);