diff mbox series

[3/9] drm/i915: Fix bits vs. bytes mixup in dbuf block size computation

Message ID 20181221171436.8218-4-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series skl+ watermark stuff | expand

Commit Message

Ville Syrjala Dec. 21, 2018, 5:14 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The spec used to say "8bpp" which someone took to mean 8 bytes per
pixel when in fact it was supposed to be 8 bits per pixel. The
spec has been updated to make it more clear now. Fix the code
to match.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Lisovskiy, Stanislav Jan. 28, 2019, 8:43 a.m. UTC | #1 
On Fri, 2018-12-21 at 19:14 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The spec used to say "8bpp" which someone took to mean 8 bytes per
> pixel when in fact it was supposed to be 8 bits per pixel. The
> spec has been updated to make it more clear now. Fix the code
> to match.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 0aac7e7b660f..55a1c577f060 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4618,7 +4618,7 @@ skl_compute_plane_wm_params(const struct
> intel_crtc_state *cstate,
>  							     intel_p
> state);
>  
>  	if (INTEL_GEN(dev_priv) >= 11 &&
> -	    fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp ==
> 8)
> +	    fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp ==
> 1)
>  		wp->dbuf_block_size = 256;
>  	else
>  		wp->dbuf_block_size = 512;

Interesting how this small misunderstanding could affect our bugs
previously.

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Matt Roper Jan. 29, 2019, 11:54 p.m. UTC | #2 
On Fri, Dec 21, 2018 at 07:14:30PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The spec used to say "8bpp" which someone took to mean 8 bytes per
> pixel when in fact it was supposed to be 8 bits per pixel. The
> spec has been updated to make it more clear now. Fix the code
> to match.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0aac7e7b660f..55a1c577f060 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4618,7 +4618,7 @@ skl_compute_plane_wm_params(const struct intel_crtc_state *cstate,
>  							     intel_pstate);
>  
>  	if (INTEL_GEN(dev_priv) >= 11 &&
> -	    fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
> +	    fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1)
>  		wp->dbuf_block_size = 256;
>  	else
>  		wp->dbuf_block_size = 512;
> -- 
> 2.19.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0aac7e7b660f..55a1c577f060 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4618,7 +4618,7 @@  skl_compute_plane_wm_params(const struct intel_crtc_state *cstate,
 							     intel_pstate);
 
 	if (INTEL_GEN(dev_priv) >= 11 &&
-	    fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
+	    fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 1)
 		wp->dbuf_block_size = 256;
 	else
 		wp->dbuf_block_size = 512;