| Message ID | 20190118140109.25261-26-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/38] drm/i915/execlists: Store the highest priority context | expand |
On 18/01/2019 14:00, Chris Wilson wrote: > As we no longer have a precise indication of requests queued to an > engine, make no presumptions and just sample the ring registers to see > if the engine is busy. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/i915_pmu.c | 47 +++++++++++---------------------- > 1 file changed, 16 insertions(+), 31 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c > index b1cb2d3cae16..452589a7e473 100644 > --- a/drivers/gpu/drm/i915/i915_pmu.c > +++ b/drivers/gpu/drm/i915/i915_pmu.c > @@ -148,14 +148,6 @@ void i915_pmu_gt_unparked(struct drm_i915_private *i915) > spin_unlock_irq(&i915->pmu.lock); > } > > -static bool grab_forcewake(struct drm_i915_private *i915, bool fw) > -{ > - if (!fw) > - intel_uncore_forcewake_get(i915, FORCEWAKE_ALL); > - > - return true; > -} > - > static void > add_sample(struct i915_pmu_sample *sample, u32 val) > { > @@ -168,7 +160,6 @@ engines_sample(struct drm_i915_private *dev_priv, unsigned int period_ns) > struct intel_engine_cs *engine; > enum intel_engine_id id; > intel_wakeref_t wakeref; > - bool fw = false; > > if ((dev_priv->pmu.enable & ENGINE_SAMPLE_MASK) == 0) > return; > @@ -180,37 +171,31 @@ engines_sample(struct drm_i915_private *dev_priv, unsigned int period_ns) > if (!wakeref) > return; > > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > for_each_engine(engine, dev_priv, id) { > - u32 current_seqno = intel_engine_get_seqno(engine); > - u32 last_seqno = intel_engine_last_submit(engine); > + typeof(engine->pmu) *pmu = &engine->pmu; Or name the struct? > u32 val; > > - val = !i915_seqno_passed(current_seqno, last_seqno); > - > - if (val) > - add_sample(&engine->pmu.sample[I915_SAMPLE_BUSY], > - period_ns); > + val = I915_READ_FW(RING_MI_MODE(engine->mmio_base)); > + if (val & MODE_IDLE) > + continue; > > - if (val && (engine->pmu.enable & > - (BIT(I915_SAMPLE_WAIT) | BIT(I915_SAMPLE_SEMA)))) { > - fw = grab_forcewake(dev_priv, fw); > + add_sample(&pmu->sample[I915_SAMPLE_BUSY], period_ns); > > + if (pmu->enable & > + (BIT(I915_SAMPLE_WAIT) | BIT(I915_SAMPLE_SEMA))) { > val = I915_READ_FW(RING_CTL(engine->mmio_base)); > - } else { > - val = 0; > - } > > - if (val & RING_WAIT) > - add_sample(&engine->pmu.sample[I915_SAMPLE_WAIT], > - period_ns); > + if (val & RING_WAIT) > + add_sample(&pmu->sample[I915_SAMPLE_WAIT], > + period_ns); > > - if (val & RING_WAIT_SEMAPHORE) > - add_sample(&engine->pmu.sample[I915_SAMPLE_SEMA], > - period_ns); > + if (val & RING_WAIT_SEMAPHORE) > + add_sample(&pmu->sample[I915_SAMPLE_SEMA], > + period_ns); > + } > } > - > - if (fw) > - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > > intel_runtime_pm_put(dev_priv, wakeref); > } > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index b1cb2d3cae16..452589a7e473 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -148,14 +148,6 @@ void i915_pmu_gt_unparked(struct drm_i915_private *i915) spin_unlock_irq(&i915->pmu.lock); } -static bool grab_forcewake(struct drm_i915_private *i915, bool fw) -{ - if (!fw) - intel_uncore_forcewake_get(i915, FORCEWAKE_ALL); - - return true; -} - static void add_sample(struct i915_pmu_sample *sample, u32 val) { @@ -168,7 +160,6 @@ engines_sample(struct drm_i915_private *dev_priv, unsigned int period_ns) struct intel_engine_cs *engine; enum intel_engine_id id; intel_wakeref_t wakeref; - bool fw = false; if ((dev_priv->pmu.enable & ENGINE_SAMPLE_MASK) == 0) return; @@ -180,37 +171,31 @@ engines_sample(struct drm_i915_private *dev_priv, unsigned int period_ns) if (!wakeref) return; + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); for_each_engine(engine, dev_priv, id) { - u32 current_seqno = intel_engine_get_seqno(engine); - u32 last_seqno = intel_engine_last_submit(engine); + typeof(engine->pmu) *pmu = &engine->pmu; u32 val; - val = !i915_seqno_passed(current_seqno, last_seqno); - - if (val) - add_sample(&engine->pmu.sample[I915_SAMPLE_BUSY], - period_ns); + val = I915_READ_FW(RING_MI_MODE(engine->mmio_base)); + if (val & MODE_IDLE) + continue; - if (val && (engine->pmu.enable & - (BIT(I915_SAMPLE_WAIT) | BIT(I915_SAMPLE_SEMA)))) { - fw = grab_forcewake(dev_priv, fw); + add_sample(&pmu->sample[I915_SAMPLE_BUSY], period_ns); + if (pmu->enable & + (BIT(I915_SAMPLE_WAIT) | BIT(I915_SAMPLE_SEMA))) { val = I915_READ_FW(RING_CTL(engine->mmio_base)); - } else { - val = 0; - } - if (val & RING_WAIT) - add_sample(&engine->pmu.sample[I915_SAMPLE_WAIT], - period_ns); + if (val & RING_WAIT) + add_sample(&pmu->sample[I915_SAMPLE_WAIT], + period_ns); - if (val & RING_WAIT_SEMAPHORE) - add_sample(&engine->pmu.sample[I915_SAMPLE_SEMA], - period_ns); + if (val & RING_WAIT_SEMAPHORE) + add_sample(&pmu->sample[I915_SAMPLE_SEMA], + period_ns); + } } - - if (fw) - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); intel_runtime_pm_put(dev_priv, wakeref); }
As we no longer have a precise indication of requests queued to an engine, make no presumptions and just sample the ring registers to see if the engine is busy. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_pmu.c | 47 +++++++++++---------------------- 1 file changed, 16 insertions(+), 31 deletions(-)