| Message ID | 20190125023005.1007-4-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/33] drm/i915/execlists: Move RPCS setup to context pin | expand |
Chris Wilson <chris@chris-wilson.co.uk> writes: > Simplify by using sizeof(u32) to convert from the index inside the HWSP > to the byte offset. This has the advantage of not only being shorter > (and so not upsetting checkpatch!) but that it matches use where we are > writing to byte addresses using other commands than MI_STORE_DWORD_IMM. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/intel_guc_submission.c | 4 ++-- > drivers/gpu/drm/i915/intel_ringbuffer.h | 10 +++++----- > 2 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c > index ab1c49b106f2..349ae5844f24 100644 > --- a/drivers/gpu/drm/i915/intel_guc_submission.c > +++ b/drivers/gpu/drm/i915/intel_guc_submission.c > @@ -666,7 +666,7 @@ static void complete_preempt_context(struct intel_engine_cs *engine) > execlists_unwind_incomplete_requests(execlists); > > wait_for_guc_preempt_report(engine); > - intel_write_status_page(engine, I915_GEM_HWS_PREEMPT_INDEX, 0); > + intel_write_status_page(engine, I915_GEM_HWS_PREEMPT, 0); > } > > /** > @@ -824,7 +824,7 @@ static void guc_submission_tasklet(unsigned long data) > } > > if (execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT) && > - intel_read_status_page(engine, I915_GEM_HWS_PREEMPT_INDEX) == > + intel_read_status_page(engine, I915_GEM_HWS_PREEMPT) == > GUC_PREEMPT_FINISHED) > complete_preempt_context(engine); > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h > index 0834e91d4ace..5ad46c2fbc0f 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -716,11 +716,11 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) > * The area from dword 0x30 to 0x3ff is available for driver usage. > */ > #define I915_GEM_HWS_INDEX 0x30 > -#define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT) > -#define I915_GEM_HWS_PREEMPT_INDEX 0x32 > -#define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT_INDEX << MI_STORE_DWORD_INDEX_SHIFT) > -#define I915_GEM_HWS_SCRATCH_INDEX 0x40 > -#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) I don't find usage nor reasoning for MI_STORE_DWORD_INDEX_SHIFT in the intel_gpu_commands.h. So it should go too. Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > +#define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX * sizeof(u32)) > +#define I915_GEM_HWS_PREEMPT 0x32 > +#define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32)) > +#define I915_GEM_HWS_SCRATCH 0x40 > +#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH * sizeof(u32)) > > #define I915_HWS_CSB_BUF0_INDEX 0x10 > #define I915_HWS_CSB_WRITE_INDEX 0x1f > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index ab1c49b106f2..349ae5844f24 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -666,7 +666,7 @@ static void complete_preempt_context(struct intel_engine_cs *engine) execlists_unwind_incomplete_requests(execlists); wait_for_guc_preempt_report(engine); - intel_write_status_page(engine, I915_GEM_HWS_PREEMPT_INDEX, 0); + intel_write_status_page(engine, I915_GEM_HWS_PREEMPT, 0); } /** @@ -824,7 +824,7 @@ static void guc_submission_tasklet(unsigned long data) } if (execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT) && - intel_read_status_page(engine, I915_GEM_HWS_PREEMPT_INDEX) == + intel_read_status_page(engine, I915_GEM_HWS_PREEMPT) == GUC_PREEMPT_FINISHED) complete_preempt_context(engine); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 0834e91d4ace..5ad46c2fbc0f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -716,11 +716,11 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) * The area from dword 0x30 to 0x3ff is available for driver usage. */ #define I915_GEM_HWS_INDEX 0x30 -#define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT) -#define I915_GEM_HWS_PREEMPT_INDEX 0x32 -#define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT_INDEX << MI_STORE_DWORD_INDEX_SHIFT) -#define I915_GEM_HWS_SCRATCH_INDEX 0x40 -#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) +#define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX * sizeof(u32)) +#define I915_GEM_HWS_PREEMPT 0x32 +#define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32)) +#define I915_GEM_HWS_SCRATCH 0x40 +#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH * sizeof(u32)) #define I915_HWS_CSB_BUF0_INDEX 0x10 #define I915_HWS_CSB_WRITE_INDEX 0x1f
Simplify by using sizeof(u32) to convert from the index inside the HWSP to the byte offset. This has the advantage of not only being shorter (and so not upsetting checkpatch!) but that it matches use where we are writing to byte addresses using other commands than MI_STORE_DWORD_IMM. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/intel_guc_submission.c | 4 ++-- drivers/gpu/drm/i915/intel_ringbuffer.h | 10 +++++----- 2 files changed, 7 insertions(+), 7 deletions(-)