From patchwork Sat Jan 26 01:22:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10782285 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 579A214E5 for ; Sat, 26 Jan 2019 01:23:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 45CC530AD4 for ; Sat, 26 Jan 2019 01:23:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 39F3D30AD6; Sat, 26 Jan 2019 01:23:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CB1AD30AD4 for ; Sat, 26 Jan 2019 01:23:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 48B816E0EB; Sat, 26 Jan 2019 01:23:13 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8232F6E0EB for ; Sat, 26 Jan 2019 01:23:09 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Jan 2019 17:23:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,523,1539673200"; d="scan'208";a="128655675" Received: from josouza-mobl.jf.intel.com ([10.24.11.86]) by FMSMGA003.fm.intel.com with ESMTP; 25 Jan 2019 17:23:08 -0800 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Date: Fri, 25 Jan 2019 17:22:56 -0800 Message-Id: <20190126012256.18360-4-jose.souza@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190126012256.18360-1-jose.souza@intel.com> References: <20190126012256.18360-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] drm/i915/psr: Print why PSR or PSR2 was not enabled in debugfs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dhinakaran Pandiyan Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP PSR needs to do some checks against the current/future CRTC state to confirm if PSR hardware can support PSR in given configuration. So lets add this information to debugfs this way we can make IGT test smarter and skip tests when a valid a know reason caused PSR to not be enabled. It will print PSR2 reason even if PSR1 is enabled as PSR2 have some additional requirements. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 13 ++++++++++++- 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 3b995f9fdc06..9ea99e9fb402 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2571,6 +2571,8 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) else status = "disabled"; seq_printf(m, "PSR mode: %s\n", status); + if (psr->disabled_reason) + seq_printf(m, "Disabled reason: %s\n", psr->disabled_reason); if (!psr->enabled) goto unlock; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0133d1da3d3c..2bedb523922d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -512,6 +512,7 @@ struct i915_psr { bool sink_not_reliable; bool irq_aux_error; u16 su_x_granularity; + const char *disabled_reason; }; enum intel_pch { diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 2c267c6501fc..a4214c133218 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -530,8 +530,10 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay; int psr_max_h = 0, psr_max_v = 0; - if (!dev_priv->psr.sink_psr2_support) + if (!dev_priv->psr.sink_psr2_support) { + dev_priv->psr.disabled_reason = "PSR2 not supported by sink"; return false; + } /* * DSC and PSR2 cannot be enabled simultaneously. If a requested @@ -540,6 +542,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, */ if (crtc_state->dsc_params.compression_enable) { DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n"); + dev_priv->psr.disabled_reason = "PSR2 cannot be enabled with DSC"; return false; } @@ -555,6 +558,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, DRM_DEBUG_KMS("PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", crtc_hdisplay, crtc_vdisplay, psr_max_h, psr_max_v); + dev_priv->psr.disabled_reason = "PSR2 cannot be enabled because resolution is to big"; return false; } @@ -567,9 +571,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, if (crtc_hdisplay % dev_priv->psr.su_x_granularity) { DRM_DEBUG_KMS("PSR2 not enabled, hdisplay(%d) not multiple of %d\n", crtc_hdisplay, dev_priv->psr.su_x_granularity); + dev_priv->psr.disabled_reason = "PSR2 SU granularity requirements not met"; return false; } + dev_priv->psr.disabled_reason = NULL; return true; } @@ -597,16 +603,19 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, */ if (dig_port->base.port != PORT_A) { DRM_DEBUG_KMS("PSR condition failed: Port not supported\n"); + dev_priv->psr.disabled_reason = "PSR not supported in port"; return; } if (dev_priv->psr.sink_not_reliable) { DRM_DEBUG_KMS("PSR sink implementation is not reliable\n"); + dev_priv->psr.disabled_reason = "PSR sink implementation is not reliable"; return; } if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); + dev_priv->psr.disabled_reason = "PSR HW do not support interlaced mode"; return; } @@ -614,6 +623,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, if (psr_setup_time < 0) { DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n", intel_dp->psr_dpcd[1]); + dev_priv->psr.disabled_reason = "PSR setup time is invalid"; return; } @@ -621,6 +631,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n", psr_setup_time); + dev_priv->psr.disabled_reason = "PSR setup time is longer than vblank"; return; }