From patchwork Thu Feb 14 14:57:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 10812911 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 52B5D13B5 for ; Thu, 14 Feb 2019 14:58:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3FECD2E907 for ; Thu, 14 Feb 2019 14:58:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 332662E908; Thu, 14 Feb 2019 14:58:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8348A2E900 for ; Thu, 14 Feb 2019 14:58:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0EA906E917; Thu, 14 Feb 2019 14:58:01 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id A97336E917 for ; Thu, 14 Feb 2019 14:58:00 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Feb 2019 06:58:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,369,1544515200"; d="scan'208";a="114920447" Received: from jhbrinke-mobl3.amr.corp.intel.com (HELO mwahaha.ger.corp.intel.com) ([10.252.11.151]) by orsmga007.jf.intel.com with ESMTP; 14 Feb 2019 06:57:58 -0800 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Thu, 14 Feb 2019 14:57:11 +0000 Message-Id: <20190214145740.14521-14-matthew.auld@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190214145740.14521-1-matthew.auld@intel.com> References: <20190214145740.14521-1-matthew.auld@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC PATCH 13/42] drm/i915: support object clearing via blitter engine X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Support clearing objects via the blitter engine. This is needed for LMEM where we need to clear the backing store before handing the object to userspace. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Abdiel Janulgue --- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_gem.c | 151 ++++++++++++++++++ drivers/gpu/drm/i915/intel_gpu_commands.h | 1 + .../gpu/drm/i915/selftests/i915_gem_object.c | 70 ++++++++ 4 files changed, 224 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a0ed000d52aa..feec3bab0f5f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2807,6 +2807,8 @@ void *i915_gem_object_alloc(struct drm_i915_private *dev_priv); void i915_gem_object_free(struct drm_i915_gem_object *obj); void i915_gem_object_init(struct drm_i915_gem_object *obj, const struct drm_i915_gem_object_ops *ops); +int i915_gem_object_clear_blt(struct i915_gem_context *ctx, + struct drm_i915_gem_object *obj); struct drm_i915_gem_object * i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size); struct drm_i915_gem_object * diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 7f044b643a75..032d4334c0f1 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4288,6 +4288,157 @@ static bool discard_backing_storage(struct drm_i915_gem_object *obj) return atomic_long_read(&obj->base.filp->f_count) == 1; } +static struct i915_vma * +__i915_gem_fill_blt(struct i915_vma *vma, u32 value) +{ + struct drm_i915_private *i915 = to_i915(vma->obj->base.dev); + const int gen = INTEL_GEN(i915); + struct drm_i915_gem_object *obj; + struct i915_vma *batch; + u32 *cmd; + int err; + + obj = i915_gem_object_create_internal(i915, PAGE_SIZE); + if (IS_ERR(obj)) + return ERR_CAST(obj); + + cmd = i915_gem_object_pin_map(obj, I915_MAP_WB); + if (IS_ERR(cmd)) { + err = PTR_ERR(cmd); + goto err; + } + + if (gen >= 8) { + *cmd++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA; + *cmd++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE; + *cmd++ = 0; + *cmd++ = vma->obj->base.size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4; + *cmd++ = lower_32_bits(vma->node.start); + *cmd++ = upper_32_bits(vma->node.start); + *cmd++ = value; + *cmd++ = MI_NOOP; + } else { + *cmd++ = COLOR_BLT_CMD | BLT_WRITE_RGBA; + *cmd++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE; + *cmd++ = vma->obj->base.size >> PAGE_SHIFT << 16 | PAGE_SIZE; + *cmd++ = vma->node.start; + *cmd++ = value; + *cmd++ = MI_NOOP; + } + + *cmd = MI_BATCH_BUFFER_END; + + i915_gem_object_unpin_map(obj); + + err = i915_gem_object_set_to_gtt_domain(obj, false); + if (err) + goto err; + + batch = i915_vma_instance(obj, vma->vm, NULL); + if (IS_ERR(batch)) { + err = PTR_ERR(batch); + goto err; + } + + err = i915_vma_pin(batch, 0, 0, PIN_USER); + if (err) + goto err; + + return batch; + +err: + i915_gem_object_put(obj); + return ERR_PTR(err); +} + +static int i915_gem_fill_blt(struct i915_gem_context *ctx, + struct i915_vma *vma, + u32 value) +{ + struct drm_i915_private *i915 = to_i915(vma->obj->base.dev); + struct intel_engine_cs *engine = i915->engine[BCS]; + struct i915_request *rq; + struct i915_vma *batch; + int flags = 0; + int err; + + err = i915_gem_object_set_to_gtt_domain(vma->obj, true); + if (err) + return err; + + rq = i915_request_alloc(engine, ctx); + if (IS_ERR(rq)) + return PTR_ERR(rq); + + batch = __i915_gem_fill_blt(vma, value); + if (IS_ERR(batch)) { + err = PTR_ERR(batch); + goto err_request; + } + + err = i915_vma_move_to_active(batch, rq, 0); + i915_vma_unpin(batch); + i915_vma_close(batch); + if (err) { + i915_gem_object_put(batch->obj); + goto err_request; + } + + i915_gem_object_set_active_reference(batch->obj); + + err = engine->emit_bb_start(rq, + batch->node.start, batch->node.size, + flags); + if (err) + goto err_request; + + err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE); + if (err) + i915_request_skip(rq, err); + +err_request: + i915_request_add(rq); + return err; +} + +static int i915_gem_object_fill_blt(struct i915_gem_context *ctx, + struct drm_i915_gem_object *obj, + u32 value) +{ + struct drm_i915_private *i915 = to_i915(obj->base.dev); + struct i915_address_space *vm = ctx->ppgtt ? &ctx->ppgtt->vm : &i915->ggtt.vm; + struct i915_vma *vma; + int err; + + lockdep_assert_held(&i915->drm.struct_mutex); + + vma = i915_vma_instance(obj, vm, NULL); + if (IS_ERR(vma)) + return PTR_ERR(vma); + + err = i915_vma_pin(vma, 0, 0, PIN_USER); + if (err) { + i915_vma_close(vma); + return err; + } + + err = i915_gem_fill_blt(ctx, vma, value); + i915_vma_unpin(vma); + if (err) + return err; + + return i915_gem_object_wait(obj, + I915_WAIT_LOCKED | + I915_WAIT_ALL, + MAX_SCHEDULE_TIMEOUT); +} + +int i915_gem_object_clear_blt(struct i915_gem_context *ctx, + struct drm_i915_gem_object *obj) +{ + return i915_gem_object_fill_blt(ctx, obj, 0); +} + static void __i915_gem_free_objects(struct drm_i915_private *i915, struct llist_node *freed) { diff --git a/drivers/gpu/drm/i915/intel_gpu_commands.h b/drivers/gpu/drm/i915/intel_gpu_commands.h index b96a31bc1080..f74ff1d095c2 100644 --- a/drivers/gpu/drm/i915/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/intel_gpu_commands.h @@ -175,6 +175,7 @@ #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2)) +#define XY_COLOR_BLT_CMD (2<<29 | 0x50<<22 | (7-2)) #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_object.c b/drivers/gpu/drm/i915/selftests/i915_gem_object.c index 395ae878e0f7..c83dc5e2f219 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_object.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_object.c @@ -628,6 +628,75 @@ static int igt_mmap_offset_exhaustion(void *arg) goto out; } +static int igt_fill_blt(void *arg) +{ + struct drm_i915_private *i915 = arg; + struct drm_i915_gem_object *obj; + struct i915_gem_context *ctx; + struct drm_file *file; + struct rnd_state prng; + IGT_TIMEOUT(end); + u32 *vaddr; + int err; + + file = mock_file(i915); + if (IS_ERR(file)) + return PTR_ERR(file); + + ctx = live_context(i915, file); + if (IS_ERR(ctx)) { + err = PTR_ERR(ctx); + goto err_file; + } + + obj = i915_gem_object_create_internal(i915, SZ_2M); + if (IS_ERR(obj)) { + err = PTR_ERR(obj); + goto err_file; + } + + vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); + if (IS_ERR(vaddr)) { + err = PTR_ERR(vaddr); + goto err_put; + } + + prandom_seed_state(&prng, i915_selftest.random_seed); + + mutex_lock(&i915->drm.struct_mutex); + + do { + u32 val = prandom_u32_state(&prng); + u32 i; + + err = i915_gem_object_fill_blt(ctx, obj, val); + if (err) + break; + + err = i915_gem_object_set_to_cpu_domain(obj, false); + if (err) + break; + + for (i = 0; i < obj->base.size / sizeof(u32); ++i) { + if (vaddr[i] != val) { + pr_err("vaddr[%d]=%u, expected=%u\n", i, + val, vaddr[i]); + err = -EINVAL; + break; + } + } + } while (!time_after(jiffies, end)); + + mutex_unlock(&i915->drm.struct_mutex); + + i915_gem_object_unpin_map(obj); +err_put: + i915_gem_object_put(obj); +err_file: + mock_file_free(i915, file); + return err; +} + int i915_gem_object_mock_selftests(void) { static const struct i915_subtest tests[] = { @@ -653,6 +722,7 @@ int i915_gem_object_live_selftests(struct drm_i915_private *i915) SUBTEST(igt_gem_huge), SUBTEST(igt_partial_tiling), SUBTEST(igt_mmap_offset_exhaustion), + SUBTEST(igt_fill_blt), }; return i915_subtests(tests, i915);