From patchwork Mon Feb 18 19:31:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 10818703 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 605611390 for ; Mon, 18 Feb 2019 19:32:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4E9FA2BBD2 for ; Mon, 18 Feb 2019 19:32:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 436702BBD0; Mon, 18 Feb 2019 19:32:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D2A0D2BBD2 for ; Mon, 18 Feb 2019 19:32:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5911C8921E; Mon, 18 Feb 2019 19:32:06 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 06C0D8921E for ; Mon, 18 Feb 2019 19:32:04 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Feb 2019 11:32:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,385,1544515200"; d="scan'208";a="135280016" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga002.jf.intel.com with SMTP; 18 Feb 2019 11:32:01 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 18 Feb 2019 21:32:01 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Mon, 18 Feb 2019 21:31:37 +0200 Message-Id: <20190218193137.22914-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190218193137.22914-1-ville.syrjala@linux.intel.com> References: <20190218193137.22914-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 7/7] drm/i915: Split ilk vs. icl csc matrix handling X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä Split the csc matrix handling to ilk+ and icl+ functions. This keeps the logic clear on what is loaded into which CSC unit on the hardware. We also fix the icl+ code to load the full->limited range conversion matrix into the output CSC rather than the pipe CSC which was used on earlier platforms. And we also turn on the pipe CSC only when the ctm is present. Signed-off-by: Ville Syrjälä Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/intel_color.c | 71 ++++++++++++++++++------------ 1 file changed, 42 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index adc5c25a6fcd..ae91a4db71cf 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -255,36 +255,19 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); bool limited_color_range = ilk_csc_limited_range(crtc_state); - enum pipe pipe = crtc->pipe; - u16 coeffs[9] = {}; - - if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || - crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) { - if (INTEL_GEN(dev_priv) >= 11) - icl_update_output_csc(crtc, ilk_csc_off_zero, - ilk_csc_coeff_rgb_to_ycbcr, - ilk_csc_postoff_rgb_to_ycbcr); - else - ilk_update_pipe_csc(crtc, ilk_csc_off_zero, - ilk_csc_coeff_rgb_to_ycbcr, - ilk_csc_postoff_rgb_to_ycbcr); - - I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode); - /* - * On pre GEN11 output CSC is not there, so with 1 pipe CSC - * RGB to YUV conversion can be done. No need to go further - */ - if (INTEL_GEN(dev_priv) < 11) - return; - } if (crtc_state->base.ctm) { - ilk_csc_convert_ctm(crtc_state, coeffs); + u16 coeff[9]; - ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeffs, + ilk_csc_convert_ctm(crtc_state, coeff); + ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff, limited_color_range ? ilk_csc_postoff_limited_range : ilk_csc_off_zero); + } else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) { + ilk_update_pipe_csc(crtc, ilk_csc_off_zero, + ilk_csc_coeff_rgb_to_ycbcr, + ilk_csc_postoff_rgb_to_ycbcr); } else if (limited_color_range) { ilk_update_pipe_csc(crtc, ilk_csc_off_zero, ilk_csc_coeff_limited_range, @@ -295,7 +278,33 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state) ilk_csc_off_zero); } - I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode); + I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode); +} + +static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + + if (crtc_state->base.ctm) { + u16 coeff[9]; + + ilk_csc_convert_ctm(crtc_state, coeff); + ilk_update_pipe_csc(crtc, ilk_csc_off_zero, + coeff, ilk_csc_off_zero); + } + + if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) { + icl_update_output_csc(crtc, ilk_csc_off_zero, + ilk_csc_coeff_rgb_to_ycbcr, + ilk_csc_postoff_rgb_to_ycbcr); + } else if (crtc_state->limited_color_range) { + icl_update_output_csc(crtc, ilk_csc_off_zero, + ilk_csc_coeff_limited_range, + ilk_csc_postoff_limited_range); + } + + I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode); } /* @@ -445,7 +454,10 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state) I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode); - ilk_load_csc_matrix(crtc_state); + if (INTEL_GEN(dev_priv) >= 11) + icl_load_csc_matrix(crtc_state); + else + ilk_load_csc_matrix(crtc_state); } static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state) @@ -843,11 +855,12 @@ int intel_color_check(struct intel_crtc_state *crtc_state) crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT; if (INTEL_GEN(dev_priv) >= 11) { - if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || - crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) + if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB || + crtc_state->limited_color_range) crtc_state->csc_mode |= ICL_OUTPUT_CSC_ENABLE; - crtc_state->csc_mode |= ICL_CSC_ENABLE; + if (crtc_state->base.ctm) + crtc_state->csc_mode |= ICL_CSC_ENABLE; } return 0;