From patchwork Wed Mar 6 01:26:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 10840287 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 36A6117E0 for ; Wed, 6 Mar 2019 01:26:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 22F512CFEF for ; Wed, 6 Mar 2019 01:26:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 15F8F2CFF7; Wed, 6 Mar 2019 01:26:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C12F32CFEF for ; Wed, 6 Mar 2019 01:26:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E10156E034; Wed, 6 Mar 2019 01:26:52 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id D579D6E034 for ; Wed, 6 Mar 2019 01:26:51 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Mar 2019 17:26:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,445,1544515200"; d="scan'208";a="149616614" Received: from ldmartin-desk.jf.intel.com ([10.24.9.41]) by fmsmga004.fm.intel.com with ESMTP; 05 Mar 2019 17:26:50 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Tue, 5 Mar 2019 17:26:33 -0800 Message-Id: <20190306012636.18619-3-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190306012636.18619-1-lucas.demarchi@intel.com> References: <20190306012636.18619-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/5] drm/i915/icl: use a function pointer for pll_write when enabling X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This allows us to share the icl_pll_enable() between the different types of PLL while allowing the caller to differentiate how to write the registers. Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 3b3de99756d6..5511bc23ea3d 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -3118,9 +3118,10 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv, static void icl_pll_enable(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll, - i915_reg_t enable_reg) + i915_reg_t enable_reg, + void (*pll_write)(struct drm_i915_private *dev_priv, + struct intel_shared_dpll *pll)) { - const enum intel_dpll_id id = pll->info->id; u32 val; val = I915_READ(enable_reg); @@ -3133,12 +3134,9 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv, */ if (intel_wait_for_register(dev_priv, enable_reg, PLL_POWER_STATE, PLL_POWER_STATE, 1)) - DRM_ERROR("PLL %d Power not enabled\n", id); + DRM_ERROR("PLL %d Power not enabled\n", pll->info->id); - if (intel_dpll_is_combophy(id) || id == DPLL_ID_ICL_TBTPLL) - icl_dpll_write(dev_priv, pll); - else - icl_mg_pll_write(dev_priv, pll); + pll_write(dev_priv, pll); /* * DVFS pre sequence would be here, but in our driver the cdclk code @@ -3152,7 +3150,7 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv, if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, PLL_LOCK, 1)) /* 600us actually. */ - DRM_ERROR("PLL %d not locked\n", id); + DRM_ERROR("PLL %d not locked\n", pll->info->id); /* DVFS post sequence would be here. See the comment above. */ } @@ -3162,7 +3160,7 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv, { i915_reg_t enable_reg = icl_pll_id_to_enable_reg(pll->info->id); - icl_pll_enable(dev_priv, pll, enable_reg); + icl_pll_enable(dev_priv, pll, enable_reg, icl_dpll_write); } static void mg_pll_enable(struct drm_i915_private *dev_priv, @@ -3171,7 +3169,7 @@ static void mg_pll_enable(struct drm_i915_private *dev_priv, i915_reg_t enable_reg = MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id)); - icl_pll_enable(dev_priv, pll, enable_reg); + icl_pll_enable(dev_priv, pll, enable_reg, icl_mg_pll_write); } static void icl_pll_disable(struct drm_i915_private *dev_priv,