| Message ID | 20190318095204.9913-2-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/22] drm/i915: Flush pages on acquisition | expand |
On 18/03/2019 09:51, Chris Wilson wrote: > We want to use intel_engine_mask_t inside i915_request.h, which means > extracting it from the general header file mess and placing it inside a > types.h. A knock on effect is that the compiler wants to warn about > type-contraction of ALL_ENGINES into intel_engine_maskt_t, so prepare > for the worst. We can't do: #define ALL_ENGINES ((intel_engine_mask_t)-1) to avoid this warning and a lot of the churn? Regards, Tvrtko > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/gvt/gvt.h | 2 +- > drivers/gpu/drm/i915/gvt/handlers.c | 2 +- > drivers/gpu/drm/i915/gvt/scheduler.c | 2 +- > drivers/gpu/drm/i915/gvt/vgpu.c | 6 +- > drivers/gpu/drm/i915/i915_drv.h | 1 - > drivers/gpu/drm/i915/i915_reset.c | 30 +++--- > drivers/gpu/drm/i915/i915_reset.h | 6 +- > drivers/gpu/drm/i915/i915_scheduler.h | 86 +--------------- > drivers/gpu/drm/i915/i915_scheduler_types.h | 98 +++++++++++++++++++ > drivers/gpu/drm/i915/i915_timeline.h | 1 + > drivers/gpu/drm/i915/i915_timeline_types.h | 3 +- > drivers/gpu/drm/i915/intel_device_info.h | 3 +- > drivers/gpu/drm/i915/intel_engine_types.h | 9 +- > .../gpu/drm/i915/selftests/i915_gem_context.c | 4 +- > .../gpu/drm/i915/selftests/intel_hangcheck.c | 2 +- > .../test_i915_scheduler_types_standalone.c | 7 ++ > 17 files changed, 147 insertions(+), 116 deletions(-) > create mode 100644 drivers/gpu/drm/i915/i915_scheduler_types.h > create mode 100644 drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index 68fecf355471..197b081769b5 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -60,6 +60,7 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o > i915-$(CONFIG_DRM_I915_WERROR) += \ > test_i915_active_types_standalone.o \ > test_i915_gem_context_types_standalone.o \ > + test_i915_scheduler_types_standalone.o \ > test_i915_timeline_types_standalone.o \ > test_intel_context_types_standalone.o \ > test_intel_engine_types_standalone.o \ > diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h > index 8bce09de4b82..c7f373566ecd 100644 > --- a/drivers/gpu/drm/i915/gvt/gvt.h > +++ b/drivers/gpu/drm/i915/gvt/gvt.h > @@ -488,7 +488,7 @@ struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, > void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); > void intel_gvt_release_vgpu(struct intel_vgpu *vgpu); > void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, > - unsigned int engine_mask); > + unsigned long engine_mask); > void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); > void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu); > void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu); > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c > index b596cb42e24e..a0d981547c9e 100644 > --- a/drivers/gpu/drm/i915/gvt/handlers.c > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > @@ -311,7 +311,7 @@ static int mul_force_wake_write(struct intel_vgpu *vgpu, > static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, > void *p_data, unsigned int bytes) > { > - unsigned int engine_mask = 0; > + unsigned long engine_mask = 0; > u32 data; > > write_vreg(vgpu, offset, p_data, bytes); > diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c > index 7550e09939ae..56a9530b4e06 100644 > --- a/drivers/gpu/drm/i915/gvt/scheduler.c > +++ b/drivers/gpu/drm/i915/gvt/scheduler.c > @@ -1137,7 +1137,7 @@ void intel_vgpu_clean_submission(struct intel_vgpu *vgpu) > * > */ > void intel_vgpu_reset_submission(struct intel_vgpu *vgpu, > - unsigned long engine_mask) > + unsigned long engine_mask) > { > struct intel_vgpu_submission *s = &vgpu->submission; > > diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c > index 314e40121e47..e734c21e7d06 100644 > --- a/drivers/gpu/drm/i915/gvt/vgpu.c > +++ b/drivers/gpu/drm/i915/gvt/vgpu.c > @@ -526,14 +526,14 @@ struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, > * GPU engines. For FLR, engine_mask is ignored. > */ > void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, > - unsigned int engine_mask) > + unsigned long engine_mask) > { > struct intel_gvt *gvt = vgpu->gvt; > struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; > - unsigned int resetting_eng = dmlr ? ALL_ENGINES : engine_mask; > + unsigned long resetting_eng = dmlr ? ALL_ENGINES : engine_mask; > > gvt_dbg_core("------------------------------------------\n"); > - gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n", > + gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08lx\n", > vgpu->id, dmlr, engine_mask); > > vgpu->resetting_eng = resetting_eng; > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 395aa9d5ba02..86080a6e0f45 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2432,7 +2432,6 @@ static inline unsigned int i915_sg_segment_size(void) > #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) > #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) > > -#define ALL_ENGINES (~0u) > #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id)) > > #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) > diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c > index 861fe083e383..b8daec7ddc06 100644 > --- a/drivers/gpu/drm/i915/i915_reset.c > +++ b/drivers/gpu/drm/i915/i915_reset.c > @@ -144,7 +144,7 @@ static void gen3_stop_engine(struct intel_engine_cs *engine) > } > > static void i915_stop_engines(struct drm_i915_private *i915, > - unsigned int engine_mask) > + unsigned long engine_mask) > { > struct intel_engine_cs *engine; > enum intel_engine_id id; > @@ -165,7 +165,7 @@ static bool i915_in_reset(struct pci_dev *pdev) > } > > static int i915_do_reset(struct drm_i915_private *i915, > - unsigned int engine_mask, > + unsigned long engine_mask, > unsigned int retry) > { > struct pci_dev *pdev = i915->drm.pdev; > @@ -194,7 +194,7 @@ static bool g4x_reset_complete(struct pci_dev *pdev) > } > > static int g33_do_reset(struct drm_i915_private *i915, > - unsigned int engine_mask, > + unsigned long engine_mask, > unsigned int retry) > { > struct pci_dev *pdev = i915->drm.pdev; > @@ -204,7 +204,7 @@ static int g33_do_reset(struct drm_i915_private *i915, > } > > static int g4x_do_reset(struct drm_i915_private *dev_priv, > - unsigned int engine_mask, > + unsigned long engine_mask, > unsigned int retry) > { > struct pci_dev *pdev = dev_priv->drm.pdev; > @@ -242,7 +242,7 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv, > } > > static int ironlake_do_reset(struct drm_i915_private *dev_priv, > - unsigned int engine_mask, > + unsigned long engine_mask, > unsigned int retry) > { > int ret; > @@ -299,7 +299,7 @@ static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv, > } > > static int gen6_reset_engines(struct drm_i915_private *i915, > - unsigned int engine_mask, > + unsigned long engine_mask, > unsigned int retry) > { > struct intel_engine_cs *engine; > @@ -425,7 +425,7 @@ static void gen11_unlock_sfc(struct drm_i915_private *dev_priv, > } > > static int gen11_reset_engines(struct drm_i915_private *i915, > - unsigned int engine_mask, > + unsigned long engine_mask, > unsigned int retry) > { > const u32 hw_engine_mask[] = { > @@ -492,7 +492,7 @@ static void gen8_engine_reset_cancel(struct intel_engine_cs *engine) > } > > static int gen8_reset_engines(struct drm_i915_private *i915, > - unsigned int engine_mask, > + unsigned long engine_mask, > unsigned int retry) > { > struct intel_engine_cs *engine; > @@ -533,7 +533,7 @@ static int gen8_reset_engines(struct drm_i915_private *i915, > } > > typedef int (*reset_func)(struct drm_i915_private *, > - unsigned int engine_mask, > + unsigned long engine_mask, > unsigned int retry); > > static reset_func intel_get_gpu_reset(struct drm_i915_private *i915) > @@ -554,7 +554,7 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *i915) > return NULL; > } > > -int intel_gpu_reset(struct drm_i915_private *i915, unsigned int engine_mask) > +int intel_gpu_reset(struct drm_i915_private *i915, unsigned long engine_mask) > { > const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1; > reset_func reset; > @@ -588,7 +588,7 @@ int intel_gpu_reset(struct drm_i915_private *i915, unsigned int engine_mask) > if (retry) > i915_stop_engines(i915, engine_mask); > > - GEM_TRACE("engine_mask=%x\n", engine_mask); > + GEM_TRACE("engine_mask=%lx\n", engine_mask); > preempt_disable(); > ret = reset(i915, engine_mask, retry); > preempt_enable(); > @@ -688,7 +688,7 @@ static void gt_revoke(struct drm_i915_private *i915) > revoke_mmaps(i915); > } > > -static int gt_reset(struct drm_i915_private *i915, unsigned int stalled_mask) > +static int gt_reset(struct drm_i915_private *i915, unsigned long stalled_mask) > { > struct intel_engine_cs *engine; > enum intel_engine_id id; > @@ -945,7 +945,7 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915) > return result; > } > > -static int do_reset(struct drm_i915_private *i915, unsigned int stalled_mask) > +static int do_reset(struct drm_i915_private *i915, unsigned long stalled_mask) > { > int err, i; > > @@ -980,7 +980,7 @@ static int do_reset(struct drm_i915_private *i915, unsigned int stalled_mask) > * - re-init display > */ > void i915_reset(struct drm_i915_private *i915, > - unsigned int stalled_mask, > + unsigned long stalled_mask, > const char *reason) > { > struct i915_gpu_error *error = &i915->gpu_error; > @@ -1222,7 +1222,7 @@ void i915_clear_error_registers(struct drm_i915_private *dev_priv) > * of a ring dump etc.). > */ > void i915_handle_error(struct drm_i915_private *i915, > - u32 engine_mask, > + unsigned long engine_mask, > unsigned long flags, > const char *fmt, ...) > { > diff --git a/drivers/gpu/drm/i915/i915_reset.h b/drivers/gpu/drm/i915/i915_reset.h > index 16f2389f656f..6d2bf7e81ac4 100644 > --- a/drivers/gpu/drm/i915/i915_reset.h > +++ b/drivers/gpu/drm/i915/i915_reset.h > @@ -17,7 +17,7 @@ struct intel_guc; > > __printf(4, 5) > void i915_handle_error(struct drm_i915_private *i915, > - u32 engine_mask, > + unsigned long engine_mask, > unsigned long flags, > const char *fmt, ...); > #define I915_ERROR_CAPTURE BIT(0) > @@ -25,7 +25,7 @@ void i915_handle_error(struct drm_i915_private *i915, > void i915_clear_error_registers(struct drm_i915_private *i915); > > void i915_reset(struct drm_i915_private *i915, > - unsigned int stalled_mask, > + unsigned long stalled_mask, > const char *reason); > int i915_reset_engine(struct intel_engine_cs *engine, > const char *reason); > @@ -41,7 +41,7 @@ int i915_terminally_wedged(struct drm_i915_private *i915); > bool intel_has_gpu_reset(struct drm_i915_private *i915); > bool intel_has_reset_engine(struct drm_i915_private *i915); > > -int intel_gpu_reset(struct drm_i915_private *i915, u32 engine_mask); > +int intel_gpu_reset(struct drm_i915_private *i915, unsigned long engine_mask); > > int intel_reset_guc(struct drm_i915_private *i915); > > diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h > index 9a1d257f3d6e..07d243acf553 100644 > --- a/drivers/gpu/drm/i915/i915_scheduler.h > +++ b/drivers/gpu/drm/i915/i915_scheduler.h > @@ -8,92 +8,10 @@ > #define _I915_SCHEDULER_H_ > > #include <linux/bitops.h> > +#include <linux/list.h> > #include <linux/kernel.h> > > -#include <uapi/drm/i915_drm.h> > - > -struct drm_i915_private; > -struct i915_request; > -struct intel_engine_cs; > - > -enum { > - I915_PRIORITY_MIN = I915_CONTEXT_MIN_USER_PRIORITY - 1, > - I915_PRIORITY_NORMAL = I915_CONTEXT_DEFAULT_PRIORITY, > - I915_PRIORITY_MAX = I915_CONTEXT_MAX_USER_PRIORITY + 1, > - > - I915_PRIORITY_INVALID = INT_MIN > -}; > - > -#define I915_USER_PRIORITY_SHIFT 3 > -#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT) > - > -#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT) > -#define I915_PRIORITY_MASK (I915_PRIORITY_COUNT - 1) > - > -#define I915_PRIORITY_WAIT ((u8)BIT(0)) > -#define I915_PRIORITY_NEWCLIENT ((u8)BIT(1)) > -#define I915_PRIORITY_NOSEMAPHORE ((u8)BIT(2)) > - > -#define __NO_PREEMPTION (I915_PRIORITY_WAIT) > - > -struct i915_sched_attr { > - /** > - * @priority: execution and service priority > - * > - * All clients are equal, but some are more equal than others! > - * > - * Requests from a context with a greater (more positive) value of > - * @priority will be executed before those with a lower @priority > - * value, forming a simple QoS. > - * > - * The &drm_i915_private.kernel_context is assigned the lowest priority. > - */ > - int priority; > -}; > - > -/* > - * "People assume that time is a strict progression of cause to effect, but > - * actually, from a nonlinear, non-subjective viewpoint, it's more like a big > - * ball of wibbly-wobbly, timey-wimey ... stuff." -The Doctor, 2015 > - * > - * Requests exist in a complex web of interdependencies. Each request > - * has to wait for some other request to complete before it is ready to be run > - * (e.g. we have to wait until the pixels have been rendering into a texture > - * before we can copy from it). We track the readiness of a request in terms > - * of fences, but we also need to keep the dependency tree for the lifetime > - * of the request (beyond the life of an individual fence). We use the tree > - * at various points to reorder the requests whilst keeping the requests > - * in order with respect to their various dependencies. > - * > - * There is no active component to the "scheduler". As we know the dependency > - * DAG of each request, we are able to insert it into a sorted queue when it > - * is ready, and are able to reorder its portion of the graph to accommodate > - * dynamic priority changes. > - */ > -struct i915_sched_node { > - struct list_head signalers_list; /* those before us, we depend upon */ > - struct list_head waiters_list; /* those after us, they depend upon us */ > - struct list_head link; > - struct i915_sched_attr attr; > - unsigned int flags; > -#define I915_SCHED_HAS_SEMAPHORE BIT(0) > -}; > - > -struct i915_dependency { > - struct i915_sched_node *signaler; > - struct list_head signal_link; > - struct list_head wait_link; > - struct list_head dfs_link; > - unsigned long flags; > -#define I915_DEPENDENCY_ALLOC BIT(0) > -}; > - > -struct i915_priolist { > - struct list_head requests[I915_PRIORITY_COUNT]; > - struct rb_node node; > - unsigned long used; > - int priority; > -}; > +#include "i915_scheduler_types.h" > > #define priolist_for_each_request(it, plist, idx) \ > for (idx = 0; idx < ARRAY_SIZE((plist)->requests); idx++) \ > diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h > new file mode 100644 > index 000000000000..5c94b3eb5c81 > --- /dev/null > +++ b/drivers/gpu/drm/i915/i915_scheduler_types.h > @@ -0,0 +1,98 @@ > +/* > + * SPDX-License-Identifier: MIT > + * > + * Copyright © 2018 Intel Corporation > + */ > + > +#ifndef _I915_SCHEDULER_TYPES_H_ > +#define _I915_SCHEDULER_TYPES_H_ > + > +#include <linux/list.h> > +#include <linux/rbtree.h> > + > +#include <uapi/drm/i915_drm.h> > + > +struct drm_i915_private; > +struct i915_request; > +struct intel_engine_cs; > + > +enum { > + I915_PRIORITY_MIN = I915_CONTEXT_MIN_USER_PRIORITY - 1, > + I915_PRIORITY_NORMAL = I915_CONTEXT_DEFAULT_PRIORITY, > + I915_PRIORITY_MAX = I915_CONTEXT_MAX_USER_PRIORITY + 1, > + > + I915_PRIORITY_INVALID = INT_MIN > +}; > + > +#define I915_USER_PRIORITY_SHIFT 3 > +#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT) > + > +#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT) > +#define I915_PRIORITY_MASK (I915_PRIORITY_COUNT - 1) > + > +#define I915_PRIORITY_WAIT ((u8)BIT(0)) > +#define I915_PRIORITY_NEWCLIENT ((u8)BIT(1)) > +#define I915_PRIORITY_NOSEMAPHORE ((u8)BIT(2)) > + > +#define __NO_PREEMPTION (I915_PRIORITY_WAIT) > + > +struct i915_sched_attr { > + /** > + * @priority: execution and service priority > + * > + * All clients are equal, but some are more equal than others! > + * > + * Requests from a context with a greater (more positive) value of > + * @priority will be executed before those with a lower @priority > + * value, forming a simple QoS. > + * > + * The &drm_i915_private.kernel_context is assigned the lowest priority. > + */ > + int priority; > +}; > + > +/* > + * "People assume that time is a strict progression of cause to effect, but > + * actually, from a nonlinear, non-subjective viewpoint, it's more like a big > + * ball of wibbly-wobbly, timey-wimey ... stuff." -The Doctor, 2015 > + * > + * Requests exist in a complex web of interdependencies. Each request > + * has to wait for some other request to complete before it is ready to be run > + * (e.g. we have to wait until the pixels have been rendering into a texture > + * before we can copy from it). We track the readiness of a request in terms > + * of fences, but we also need to keep the dependency tree for the lifetime > + * of the request (beyond the life of an individual fence). We use the tree > + * at various points to reorder the requests whilst keeping the requests > + * in order with respect to their various dependencies. > + * > + * There is no active component to the "scheduler". As we know the dependency > + * DAG of each request, we are able to insert it into a sorted queue when it > + * is ready, and are able to reorder its portion of the graph to accommodate > + * dynamic priority changes. > + */ > +struct i915_sched_node { > + struct list_head signalers_list; /* those before us, we depend upon */ > + struct list_head waiters_list; /* those after us, they depend upon us */ > + struct list_head link; > + struct i915_sched_attr attr; > + unsigned int flags; > +#define I915_SCHED_HAS_SEMAPHORE BIT(0) > +}; > + > +struct i915_dependency { > + struct i915_sched_node *signaler; > + struct list_head signal_link; > + struct list_head wait_link; > + struct list_head dfs_link; > + unsigned long flags; > +#define I915_DEPENDENCY_ALLOC BIT(0) > +}; > + > +struct i915_priolist { > + struct list_head requests[I915_PRIORITY_COUNT]; > + struct rb_node node; > + unsigned long used; > + int priority; > +}; > + > +#endif /* _I915_SCHEDULER_TYPES_H_ */ > diff --git a/drivers/gpu/drm/i915/i915_timeline.h b/drivers/gpu/drm/i915/i915_timeline.h > index 9126c8206490..454aa72aee18 100644 > --- a/drivers/gpu/drm/i915/i915_timeline.h > +++ b/drivers/gpu/drm/i915/i915_timeline.h > @@ -27,6 +27,7 @@ > > #include <linux/lockdep.h> > > +#include "i915_active.h" > #include "i915_syncmap.h" > #include "i915_timeline_types.h" > > diff --git a/drivers/gpu/drm/i915/i915_timeline_types.h b/drivers/gpu/drm/i915/i915_timeline_types.h > index 8ff146dc05ba..d42053544d7c 100644 > --- a/drivers/gpu/drm/i915/i915_timeline_types.h > +++ b/drivers/gpu/drm/i915/i915_timeline_types.h > @@ -9,9 +9,10 @@ > > #include <linux/list.h> > #include <linux/kref.h> > +#include <linux/mutex.h> > #include <linux/types.h> > > -#include "i915_active.h" > +#include "i915_active_types.h" > > struct drm_i915_private; > struct i915_vma; > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index 6234570a9b17..d20c33a10c11 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -27,6 +27,7 @@ > > #include <uapi/drm/i915_drm.h> > > +#include "intel_engine_types.h" > #include "intel_display.h" > > struct drm_printer; > @@ -149,8 +150,6 @@ struct sseu_dev_info { > u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES]; > }; > > -typedef u8 intel_engine_mask_t; > - > struct intel_device_info { > u16 gen_mask; > > diff --git a/drivers/gpu/drm/i915/intel_engine_types.h b/drivers/gpu/drm/i915/intel_engine_types.h > index b0aa1f0d4e47..79a166b9a81b 100644 > --- a/drivers/gpu/drm/i915/intel_engine_types.h > +++ b/drivers/gpu/drm/i915/intel_engine_types.h > @@ -12,8 +12,10 @@ > #include <linux/list.h> > #include <linux/types.h> > > +#include "i915_gem.h" > +#include "i915_scheduler_types.h" > +#include "i915_selftest.h" > #include "i915_timeline_types.h" > -#include "intel_device_info.h" > #include "intel_workarounds_types.h" > > #include "i915_gem_batch_pool.h" > @@ -24,11 +26,16 @@ > > #define I915_CMD_HASH_ORDER 9 > > +struct dma_fence; > struct drm_i915_reg_table; > struct i915_gem_context; > struct i915_request; > struct i915_sched_attr; > > +typedef u8 intel_engine_mask_t; > +#define ALL_ENGINES (~0ul) > +#define INIT_ALL_ENGINES(x) (x) = (intel_engine_mask_t)(ALL_ENGINES) > + > struct intel_hw_status_page { > struct i915_vma *vma; > u32 *addr; > diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c > index 0759a90c0d5a..f18c78ebff07 100644 > --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c > @@ -1466,7 +1466,7 @@ static int igt_vm_isolation(void *arg) > } > > static __maybe_unused const char * > -__engine_name(struct drm_i915_private *i915, unsigned int engines) > +__engine_name(struct drm_i915_private *i915, unsigned long engines) > { > struct intel_engine_cs *engine; > unsigned int tmp; > @@ -1482,7 +1482,7 @@ __engine_name(struct drm_i915_private *i915, unsigned int engines) > > static int __igt_switch_to_kernel_context(struct drm_i915_private *i915, > struct i915_gem_context *ctx, > - unsigned int engines) > + unsigned long engines) > { > struct intel_engine_cs *engine; > unsigned int tmp; > diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c > index 76b4fa150f2e..05a7b9b9a1de 100644 > --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c > +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c > @@ -1124,7 +1124,7 @@ static int igt_reset_engines(void *arg) > return 0; > } > > -static u32 fake_hangcheck(struct drm_i915_private *i915, u32 mask) > +static u32 fake_hangcheck(struct drm_i915_private *i915, unsigned long mask) > { > u32 count = i915_reset_count(&i915->gpu_error); > > diff --git a/drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c b/drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c > new file mode 100644 > index 000000000000..8afa2c3719fb > --- /dev/null > +++ b/drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c > @@ -0,0 +1,7 @@ > +/* > + * SPDX-License-Identifier: MIT > + * > + * Copyright © 2019 Intel Corporation > + */ > + > +#include "i915_scheduler_types.h" >
Quoting Tvrtko Ursulin (2019-03-18 10:21:41) > > On 18/03/2019 09:51, Chris Wilson wrote: > > We want to use intel_engine_mask_t inside i915_request.h, which means > > extracting it from the general header file mess and placing it inside a > > types.h. A knock on effect is that the compiler wants to warn about > > type-contraction of ALL_ENGINES into intel_engine_maskt_t, so prepare > > for the worst. > > We can't do: > > #define ALL_ENGINES ((intel_engine_mask_t)-1) > > to avoid this warning and a lot of the churn? The churn is a lot of type fixing which needs to be done at some point. I'm not keen on passing the contracted intel_engine_mask_t, and ALL_ENGINES is not all bits set. -Chris
On 18/03/2019 10:40, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2019-03-18 10:21:41) >> >> On 18/03/2019 09:51, Chris Wilson wrote: >>> We want to use intel_engine_mask_t inside i915_request.h, which means >>> extracting it from the general header file mess and placing it inside a >>> types.h. A knock on effect is that the compiler wants to warn about >>> type-contraction of ALL_ENGINES into intel_engine_maskt_t, so prepare >>> for the worst. >> >> We can't do: >> >> #define ALL_ENGINES ((intel_engine_mask_t)-1) >> >> to avoid this warning and a lot of the churn? > > The churn is a lot of type fixing which needs to be done at some point. > I'm not keen on passing the contracted intel_engine_mask_t, and > ALL_ENGINES is not all bits set. It is all bit set in intel_engine_mask_t. ;) I forgot what was your argument against using it in function arguments. Perhaps because it is pointless.. I regret adding this typedef even more now. Regards, Tvrtko
Quoting Tvrtko Ursulin (2019-03-18 10:48:42) > > On 18/03/2019 10:40, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2019-03-18 10:21:41) > >> > >> On 18/03/2019 09:51, Chris Wilson wrote: > >>> We want to use intel_engine_mask_t inside i915_request.h, which means > >>> extracting it from the general header file mess and placing it inside a > >>> types.h. A knock on effect is that the compiler wants to warn about > >>> type-contraction of ALL_ENGINES into intel_engine_maskt_t, so prepare > >>> for the worst. > >> > >> We can't do: > >> > >> #define ALL_ENGINES ((intel_engine_mask_t)-1) > >> > >> to avoid this warning and a lot of the churn? > > > > The churn is a lot of type fixing which needs to be done at some point. > > I'm not keen on passing the contracted intel_engine_mask_t, and > > ALL_ENGINES is not all bits set. > > It is all bit set in intel_engine_mask_t. ;) I forgot what was your > argument against using it in function arguments. Perhaps because it is > pointless.. I regret adding this typedef even more now. I made it all intel_engine_mask_t, add/remove: 0/0 grow/shrink: 16/24 up/down: 111/-95 (16) Function old new delta workload_thread 4244 4274 +30 gen6_reset_engines 200 217 +17 intel_gpu_reset 632 646 +14 __igt_switch_to_kernel_context 399 412 +13 workload_thread.cold 1426 1436 +10 intel_gvt_reset_vgpu_locked 316 321 +5 __igt_switch_to_kernel_context.cold 126 131 +5 ring_mode_mmio_write 202 206 +4 init_execlist 13 17 +4 intel_vgpu_select_submission_ops 210 212 +2 intel_vgpu_reset_submission 49 51 +2 reset_execlist 210 211 +1 live_gpu_reset_gt_engine_workarounds.part 175 176 +1 i915_wedged_set 131 132 +1 i915_gem_init 1527 1528 +1 clean_execlist 130 131 +1 i915_capture_error_state 337 336 -1 context_barrier_task.constprop 369 368 -1 intel_vgpu_clean_submission 144 142 -2 intel_gvt_release_vgpu 60 58 -2 intel_engines_sanitize 115 113 -2 igt_wedged_reset 101 99 -2 igt_switch_to_kernel_context 240 238 -2 igt_reset_wait 340 338 -2 igt_reset_nop 442 440 -2 igt_global_reset 85 83 -2 i915_gem_resume 207 205 -2 i915_drop_caches_set 572 570 -2 __i915_gem_set_wedged.part 354 352 -2 ring_request_alloc 1887 1884 -3 igt_atomic_reset 407 404 -3 i915_gem_switch_to_kernel_context 629 626 -3 gen8_reset_engines 927 924 -3 gen6_alloc_va_range 641 638 -3 pd_vma_bind 245 241 -4 i915_reset 903 896 -7 i915_handle_error 711 704 -7 context_barrier_inject_fault 8 1 -7 mock_context_barrier 429 415 -14 gdrst_mmio_write 164 147 -17 so bizarre gcc is bizarre. Would you rather see this with universal intel_engine_mask_t? -Chris
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 68fecf355471..197b081769b5 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -60,6 +60,7 @@ i915-$(CONFIG_PERF_EVENTS) += i915_pmu.o i915-$(CONFIG_DRM_I915_WERROR) += \ test_i915_active_types_standalone.o \ test_i915_gem_context_types_standalone.o \ + test_i915_scheduler_types_standalone.o \ test_i915_timeline_types_standalone.o \ test_intel_context_types_standalone.o \ test_intel_engine_types_standalone.o \ diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 8bce09de4b82..c7f373566ecd 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -488,7 +488,7 @@ struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); void intel_gvt_release_vgpu(struct intel_vgpu *vgpu); void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, - unsigned int engine_mask); + unsigned long engine_mask); void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu); void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu); diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index b596cb42e24e..a0d981547c9e 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -311,7 +311,7 @@ static int mul_force_wake_write(struct intel_vgpu *vgpu, static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { - unsigned int engine_mask = 0; + unsigned long engine_mask = 0; u32 data; write_vreg(vgpu, offset, p_data, bytes); diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 7550e09939ae..56a9530b4e06 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -1137,7 +1137,7 @@ void intel_vgpu_clean_submission(struct intel_vgpu *vgpu) * */ void intel_vgpu_reset_submission(struct intel_vgpu *vgpu, - unsigned long engine_mask) + unsigned long engine_mask) { struct intel_vgpu_submission *s = &vgpu->submission; diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c index 314e40121e47..e734c21e7d06 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c @@ -526,14 +526,14 @@ struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, * GPU engines. For FLR, engine_mask is ignored. */ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, - unsigned int engine_mask) + unsigned long engine_mask) { struct intel_gvt *gvt = vgpu->gvt; struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; - unsigned int resetting_eng = dmlr ? ALL_ENGINES : engine_mask; + unsigned long resetting_eng = dmlr ? ALL_ENGINES : engine_mask; gvt_dbg_core("------------------------------------------\n"); - gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n", + gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08lx\n", vgpu->id, dmlr, engine_mask); vgpu->resetting_eng = resetting_eng; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 395aa9d5ba02..86080a6e0f45 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2432,7 +2432,6 @@ static inline unsigned int i915_sg_segment_size(void) #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) -#define ALL_ENGINES (~0u) #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id)) #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c index 861fe083e383..b8daec7ddc06 100644 --- a/drivers/gpu/drm/i915/i915_reset.c +++ b/drivers/gpu/drm/i915/i915_reset.c @@ -144,7 +144,7 @@ static void gen3_stop_engine(struct intel_engine_cs *engine) } static void i915_stop_engines(struct drm_i915_private *i915, - unsigned int engine_mask) + unsigned long engine_mask) { struct intel_engine_cs *engine; enum intel_engine_id id; @@ -165,7 +165,7 @@ static bool i915_in_reset(struct pci_dev *pdev) } static int i915_do_reset(struct drm_i915_private *i915, - unsigned int engine_mask, + unsigned long engine_mask, unsigned int retry) { struct pci_dev *pdev = i915->drm.pdev; @@ -194,7 +194,7 @@ static bool g4x_reset_complete(struct pci_dev *pdev) } static int g33_do_reset(struct drm_i915_private *i915, - unsigned int engine_mask, + unsigned long engine_mask, unsigned int retry) { struct pci_dev *pdev = i915->drm.pdev; @@ -204,7 +204,7 @@ static int g33_do_reset(struct drm_i915_private *i915, } static int g4x_do_reset(struct drm_i915_private *dev_priv, - unsigned int engine_mask, + unsigned long engine_mask, unsigned int retry) { struct pci_dev *pdev = dev_priv->drm.pdev; @@ -242,7 +242,7 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv, } static int ironlake_do_reset(struct drm_i915_private *dev_priv, - unsigned int engine_mask, + unsigned long engine_mask, unsigned int retry) { int ret; @@ -299,7 +299,7 @@ static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv, } static int gen6_reset_engines(struct drm_i915_private *i915, - unsigned int engine_mask, + unsigned long engine_mask, unsigned int retry) { struct intel_engine_cs *engine; @@ -425,7 +425,7 @@ static void gen11_unlock_sfc(struct drm_i915_private *dev_priv, } static int gen11_reset_engines(struct drm_i915_private *i915, - unsigned int engine_mask, + unsigned long engine_mask, unsigned int retry) { const u32 hw_engine_mask[] = { @@ -492,7 +492,7 @@ static void gen8_engine_reset_cancel(struct intel_engine_cs *engine) } static int gen8_reset_engines(struct drm_i915_private *i915, - unsigned int engine_mask, + unsigned long engine_mask, unsigned int retry) { struct intel_engine_cs *engine; @@ -533,7 +533,7 @@ static int gen8_reset_engines(struct drm_i915_private *i915, } typedef int (*reset_func)(struct drm_i915_private *, - unsigned int engine_mask, + unsigned long engine_mask, unsigned int retry); static reset_func intel_get_gpu_reset(struct drm_i915_private *i915) @@ -554,7 +554,7 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *i915) return NULL; } -int intel_gpu_reset(struct drm_i915_private *i915, unsigned int engine_mask) +int intel_gpu_reset(struct drm_i915_private *i915, unsigned long engine_mask) { const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1; reset_func reset; @@ -588,7 +588,7 @@ int intel_gpu_reset(struct drm_i915_private *i915, unsigned int engine_mask) if (retry) i915_stop_engines(i915, engine_mask); - GEM_TRACE("engine_mask=%x\n", engine_mask); + GEM_TRACE("engine_mask=%lx\n", engine_mask); preempt_disable(); ret = reset(i915, engine_mask, retry); preempt_enable(); @@ -688,7 +688,7 @@ static void gt_revoke(struct drm_i915_private *i915) revoke_mmaps(i915); } -static int gt_reset(struct drm_i915_private *i915, unsigned int stalled_mask) +static int gt_reset(struct drm_i915_private *i915, unsigned long stalled_mask) { struct intel_engine_cs *engine; enum intel_engine_id id; @@ -945,7 +945,7 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915) return result; } -static int do_reset(struct drm_i915_private *i915, unsigned int stalled_mask) +static int do_reset(struct drm_i915_private *i915, unsigned long stalled_mask) { int err, i; @@ -980,7 +980,7 @@ static int do_reset(struct drm_i915_private *i915, unsigned int stalled_mask) * - re-init display */ void i915_reset(struct drm_i915_private *i915, - unsigned int stalled_mask, + unsigned long stalled_mask, const char *reason) { struct i915_gpu_error *error = &i915->gpu_error; @@ -1222,7 +1222,7 @@ void i915_clear_error_registers(struct drm_i915_private *dev_priv) * of a ring dump etc.). */ void i915_handle_error(struct drm_i915_private *i915, - u32 engine_mask, + unsigned long engine_mask, unsigned long flags, const char *fmt, ...) { diff --git a/drivers/gpu/drm/i915/i915_reset.h b/drivers/gpu/drm/i915/i915_reset.h index 16f2389f656f..6d2bf7e81ac4 100644 --- a/drivers/gpu/drm/i915/i915_reset.h +++ b/drivers/gpu/drm/i915/i915_reset.h @@ -17,7 +17,7 @@ struct intel_guc; __printf(4, 5) void i915_handle_error(struct drm_i915_private *i915, - u32 engine_mask, + unsigned long engine_mask, unsigned long flags, const char *fmt, ...); #define I915_ERROR_CAPTURE BIT(0) @@ -25,7 +25,7 @@ void i915_handle_error(struct drm_i915_private *i915, void i915_clear_error_registers(struct drm_i915_private *i915); void i915_reset(struct drm_i915_private *i915, - unsigned int stalled_mask, + unsigned long stalled_mask, const char *reason); int i915_reset_engine(struct intel_engine_cs *engine, const char *reason); @@ -41,7 +41,7 @@ int i915_terminally_wedged(struct drm_i915_private *i915); bool intel_has_gpu_reset(struct drm_i915_private *i915); bool intel_has_reset_engine(struct drm_i915_private *i915); -int intel_gpu_reset(struct drm_i915_private *i915, u32 engine_mask); +int intel_gpu_reset(struct drm_i915_private *i915, unsigned long engine_mask); int intel_reset_guc(struct drm_i915_private *i915); diff --git a/drivers/gpu/drm/i915/i915_scheduler.h b/drivers/gpu/drm/i915/i915_scheduler.h index 9a1d257f3d6e..07d243acf553 100644 --- a/drivers/gpu/drm/i915/i915_scheduler.h +++ b/drivers/gpu/drm/i915/i915_scheduler.h @@ -8,92 +8,10 @@ #define _I915_SCHEDULER_H_ #include <linux/bitops.h> +#include <linux/list.h> #include <linux/kernel.h> -#include <uapi/drm/i915_drm.h> - -struct drm_i915_private; -struct i915_request; -struct intel_engine_cs; - -enum { - I915_PRIORITY_MIN = I915_CONTEXT_MIN_USER_PRIORITY - 1, - I915_PRIORITY_NORMAL = I915_CONTEXT_DEFAULT_PRIORITY, - I915_PRIORITY_MAX = I915_CONTEXT_MAX_USER_PRIORITY + 1, - - I915_PRIORITY_INVALID = INT_MIN -}; - -#define I915_USER_PRIORITY_SHIFT 3 -#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT) - -#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT) -#define I915_PRIORITY_MASK (I915_PRIORITY_COUNT - 1) - -#define I915_PRIORITY_WAIT ((u8)BIT(0)) -#define I915_PRIORITY_NEWCLIENT ((u8)BIT(1)) -#define I915_PRIORITY_NOSEMAPHORE ((u8)BIT(2)) - -#define __NO_PREEMPTION (I915_PRIORITY_WAIT) - -struct i915_sched_attr { - /** - * @priority: execution and service priority - * - * All clients are equal, but some are more equal than others! - * - * Requests from a context with a greater (more positive) value of - * @priority will be executed before those with a lower @priority - * value, forming a simple QoS. - * - * The &drm_i915_private.kernel_context is assigned the lowest priority. - */ - int priority; -}; - -/* - * "People assume that time is a strict progression of cause to effect, but - * actually, from a nonlinear, non-subjective viewpoint, it's more like a big - * ball of wibbly-wobbly, timey-wimey ... stuff." -The Doctor, 2015 - * - * Requests exist in a complex web of interdependencies. Each request - * has to wait for some other request to complete before it is ready to be run - * (e.g. we have to wait until the pixels have been rendering into a texture - * before we can copy from it). We track the readiness of a request in terms - * of fences, but we also need to keep the dependency tree for the lifetime - * of the request (beyond the life of an individual fence). We use the tree - * at various points to reorder the requests whilst keeping the requests - * in order with respect to their various dependencies. - * - * There is no active component to the "scheduler". As we know the dependency - * DAG of each request, we are able to insert it into a sorted queue when it - * is ready, and are able to reorder its portion of the graph to accommodate - * dynamic priority changes. - */ -struct i915_sched_node { - struct list_head signalers_list; /* those before us, we depend upon */ - struct list_head waiters_list; /* those after us, they depend upon us */ - struct list_head link; - struct i915_sched_attr attr; - unsigned int flags; -#define I915_SCHED_HAS_SEMAPHORE BIT(0) -}; - -struct i915_dependency { - struct i915_sched_node *signaler; - struct list_head signal_link; - struct list_head wait_link; - struct list_head dfs_link; - unsigned long flags; -#define I915_DEPENDENCY_ALLOC BIT(0) -}; - -struct i915_priolist { - struct list_head requests[I915_PRIORITY_COUNT]; - struct rb_node node; - unsigned long used; - int priority; -}; +#include "i915_scheduler_types.h" #define priolist_for_each_request(it, plist, idx) \ for (idx = 0; idx < ARRAY_SIZE((plist)->requests); idx++) \ diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h new file mode 100644 index 000000000000..5c94b3eb5c81 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_scheduler_types.h @@ -0,0 +1,98 @@ +/* + * SPDX-License-Identifier: MIT + * + * Copyright © 2018 Intel Corporation + */ + +#ifndef _I915_SCHEDULER_TYPES_H_ +#define _I915_SCHEDULER_TYPES_H_ + +#include <linux/list.h> +#include <linux/rbtree.h> + +#include <uapi/drm/i915_drm.h> + +struct drm_i915_private; +struct i915_request; +struct intel_engine_cs; + +enum { + I915_PRIORITY_MIN = I915_CONTEXT_MIN_USER_PRIORITY - 1, + I915_PRIORITY_NORMAL = I915_CONTEXT_DEFAULT_PRIORITY, + I915_PRIORITY_MAX = I915_CONTEXT_MAX_USER_PRIORITY + 1, + + I915_PRIORITY_INVALID = INT_MIN +}; + +#define I915_USER_PRIORITY_SHIFT 3 +#define I915_USER_PRIORITY(x) ((x) << I915_USER_PRIORITY_SHIFT) + +#define I915_PRIORITY_COUNT BIT(I915_USER_PRIORITY_SHIFT) +#define I915_PRIORITY_MASK (I915_PRIORITY_COUNT - 1) + +#define I915_PRIORITY_WAIT ((u8)BIT(0)) +#define I915_PRIORITY_NEWCLIENT ((u8)BIT(1)) +#define I915_PRIORITY_NOSEMAPHORE ((u8)BIT(2)) + +#define __NO_PREEMPTION (I915_PRIORITY_WAIT) + +struct i915_sched_attr { + /** + * @priority: execution and service priority + * + * All clients are equal, but some are more equal than others! + * + * Requests from a context with a greater (more positive) value of + * @priority will be executed before those with a lower @priority + * value, forming a simple QoS. + * + * The &drm_i915_private.kernel_context is assigned the lowest priority. + */ + int priority; +}; + +/* + * "People assume that time is a strict progression of cause to effect, but + * actually, from a nonlinear, non-subjective viewpoint, it's more like a big + * ball of wibbly-wobbly, timey-wimey ... stuff." -The Doctor, 2015 + * + * Requests exist in a complex web of interdependencies. Each request + * has to wait for some other request to complete before it is ready to be run + * (e.g. we have to wait until the pixels have been rendering into a texture + * before we can copy from it). We track the readiness of a request in terms + * of fences, but we also need to keep the dependency tree for the lifetime + * of the request (beyond the life of an individual fence). We use the tree + * at various points to reorder the requests whilst keeping the requests + * in order with respect to their various dependencies. + * + * There is no active component to the "scheduler". As we know the dependency + * DAG of each request, we are able to insert it into a sorted queue when it + * is ready, and are able to reorder its portion of the graph to accommodate + * dynamic priority changes. + */ +struct i915_sched_node { + struct list_head signalers_list; /* those before us, we depend upon */ + struct list_head waiters_list; /* those after us, they depend upon us */ + struct list_head link; + struct i915_sched_attr attr; + unsigned int flags; +#define I915_SCHED_HAS_SEMAPHORE BIT(0) +}; + +struct i915_dependency { + struct i915_sched_node *signaler; + struct list_head signal_link; + struct list_head wait_link; + struct list_head dfs_link; + unsigned long flags; +#define I915_DEPENDENCY_ALLOC BIT(0) +}; + +struct i915_priolist { + struct list_head requests[I915_PRIORITY_COUNT]; + struct rb_node node; + unsigned long used; + int priority; +}; + +#endif /* _I915_SCHEDULER_TYPES_H_ */ diff --git a/drivers/gpu/drm/i915/i915_timeline.h b/drivers/gpu/drm/i915/i915_timeline.h index 9126c8206490..454aa72aee18 100644 --- a/drivers/gpu/drm/i915/i915_timeline.h +++ b/drivers/gpu/drm/i915/i915_timeline.h @@ -27,6 +27,7 @@ #include <linux/lockdep.h> +#include "i915_active.h" #include "i915_syncmap.h" #include "i915_timeline_types.h" diff --git a/drivers/gpu/drm/i915/i915_timeline_types.h b/drivers/gpu/drm/i915/i915_timeline_types.h index 8ff146dc05ba..d42053544d7c 100644 --- a/drivers/gpu/drm/i915/i915_timeline_types.h +++ b/drivers/gpu/drm/i915/i915_timeline_types.h @@ -9,9 +9,10 @@ #include <linux/list.h> #include <linux/kref.h> +#include <linux/mutex.h> #include <linux/types.h> -#include "i915_active.h" +#include "i915_active_types.h" struct drm_i915_private; struct i915_vma; diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 6234570a9b17..d20c33a10c11 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -27,6 +27,7 @@ #include <uapi/drm/i915_drm.h> +#include "intel_engine_types.h" #include "intel_display.h" struct drm_printer; @@ -149,8 +150,6 @@ struct sseu_dev_info { u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES]; }; -typedef u8 intel_engine_mask_t; - struct intel_device_info { u16 gen_mask; diff --git a/drivers/gpu/drm/i915/intel_engine_types.h b/drivers/gpu/drm/i915/intel_engine_types.h index b0aa1f0d4e47..79a166b9a81b 100644 --- a/drivers/gpu/drm/i915/intel_engine_types.h +++ b/drivers/gpu/drm/i915/intel_engine_types.h @@ -12,8 +12,10 @@ #include <linux/list.h> #include <linux/types.h> +#include "i915_gem.h" +#include "i915_scheduler_types.h" +#include "i915_selftest.h" #include "i915_timeline_types.h" -#include "intel_device_info.h" #include "intel_workarounds_types.h" #include "i915_gem_batch_pool.h" @@ -24,11 +26,16 @@ #define I915_CMD_HASH_ORDER 9 +struct dma_fence; struct drm_i915_reg_table; struct i915_gem_context; struct i915_request; struct i915_sched_attr; +typedef u8 intel_engine_mask_t; +#define ALL_ENGINES (~0ul) +#define INIT_ALL_ENGINES(x) (x) = (intel_engine_mask_t)(ALL_ENGINES) + struct intel_hw_status_page { struct i915_vma *vma; u32 *addr; diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c index 0759a90c0d5a..f18c78ebff07 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c @@ -1466,7 +1466,7 @@ static int igt_vm_isolation(void *arg) } static __maybe_unused const char * -__engine_name(struct drm_i915_private *i915, unsigned int engines) +__engine_name(struct drm_i915_private *i915, unsigned long engines) { struct intel_engine_cs *engine; unsigned int tmp; @@ -1482,7 +1482,7 @@ __engine_name(struct drm_i915_private *i915, unsigned int engines) static int __igt_switch_to_kernel_context(struct drm_i915_private *i915, struct i915_gem_context *ctx, - unsigned int engines) + unsigned long engines) { struct intel_engine_cs *engine; unsigned int tmp; diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index 76b4fa150f2e..05a7b9b9a1de 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -1124,7 +1124,7 @@ static int igt_reset_engines(void *arg) return 0; } -static u32 fake_hangcheck(struct drm_i915_private *i915, u32 mask) +static u32 fake_hangcheck(struct drm_i915_private *i915, unsigned long mask) { u32 count = i915_reset_count(&i915->gpu_error); diff --git a/drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c b/drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c new file mode 100644 index 000000000000..8afa2c3719fb --- /dev/null +++ b/drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c @@ -0,0 +1,7 @@ +/* + * SPDX-License-Identifier: MIT + * + * Copyright © 2019 Intel Corporation + */ + +#include "i915_scheduler_types.h"
We want to use intel_engine_mask_t inside i915_request.h, which means extracting it from the general header file mess and placing it inside a types.h. A knock on effect is that the compiler wants to warn about type-contraction of ALL_ENGINES into intel_engine_maskt_t, so prepare for the worst. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gvt/gvt.h | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 2 +- drivers/gpu/drm/i915/gvt/scheduler.c | 2 +- drivers/gpu/drm/i915/gvt/vgpu.c | 6 +- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/i915_reset.c | 30 +++--- drivers/gpu/drm/i915/i915_reset.h | 6 +- drivers/gpu/drm/i915/i915_scheduler.h | 86 +--------------- drivers/gpu/drm/i915/i915_scheduler_types.h | 98 +++++++++++++++++++ drivers/gpu/drm/i915/i915_timeline.h | 1 + drivers/gpu/drm/i915/i915_timeline_types.h | 3 +- drivers/gpu/drm/i915/intel_device_info.h | 3 +- drivers/gpu/drm/i915/intel_engine_types.h | 9 +- .../gpu/drm/i915/selftests/i915_gem_context.c | 4 +- .../gpu/drm/i915/selftests/intel_hangcheck.c | 2 +- .../test_i915_scheduler_types_standalone.c | 7 ++ 17 files changed, 147 insertions(+), 116 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_scheduler_types.h create mode 100644 drivers/gpu/drm/i915/test_i915_scheduler_types_standalone.c