From patchwork Tue Apr 9 21:31:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fernando Pacheco X-Patchwork-Id: 10892455 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0A9EF17E1 for ; Tue, 9 Apr 2019 21:33:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EB1C528984 for ; Tue, 9 Apr 2019 21:33:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DE91928985; Tue, 9 Apr 2019 21:33:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 78E3028984 for ; Tue, 9 Apr 2019 21:33:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EFA0C89256; Tue, 9 Apr 2019 21:33:26 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2A39689256 for ; Tue, 9 Apr 2019 21:33:26 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Apr 2019 14:33:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,330,1549958400"; d="scan'208";a="129984968" Received: from pachecof-ubuntu.fm.intel.com ([10.1.27.26]) by orsmga007.jf.intel.com with ESMTP; 09 Apr 2019 14:33:25 -0700 From: Fernando Pacheco To: intel-gfx@lists.freedesktop.org Date: Tue, 9 Apr 2019 14:31:00 -0700 Message-Id: <20190409213102.30124-3-fernando.pacheco@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190409213102.30124-1-fernando.pacheco@intel.com> References: <20190409213102.30124-1-fernando.pacheco@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915/uc: Reserve upper range of GGTT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP GuC and HuC depend on struct_mutex for device reinitialization. Moving away from this dependency requires perma-pinning the firmware images in GGTT. The upper portion of the GuC address space has a sizeable hole (several MB) that is inaccessible by GuC. Reserve this range within GGTT as it can comfortably hold GuC/HuC firmware images. Signed-off-by: Fernando Pacheco --- drivers/gpu/drm/i915/i915_gem_gtt.c | 25 ++++++++++++++++++++++--- drivers/gpu/drm/i915/i915_gem_gtt.h | 1 + drivers/gpu/drm/i915/intel_guc.h | 11 +++++++++++ 3 files changed, 34 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 736c845eb77f..30f294a07e6d 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2747,6 +2747,18 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) if (ret) return ret; + /* Reserve a mappable slot for our lockless uC firmware load */ + if (USES_GUC(dev_priv)) { + ret = drm_mm_insert_node_in_range(&ggtt->vm.mm, &ggtt->uc_fw, + GUC_GGTT_FW_SIZE, 0, + I915_COLOR_UNEVICTABLE, + GUC_GGTT_FW_START, + GUC_GGTT_FW_END, + DRM_MM_INSERT_LOW); + if (ret) + goto err_node; + } + /* Clear any non-preallocated blocks */ drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) { DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", @@ -2761,12 +2773,15 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) { ret = i915_gem_init_aliasing_ppgtt(dev_priv); if (ret) - goto err; + goto err_appgtt; } return 0; -err: +err_appgtt: + if (USES_GUC(dev_priv)) + drm_mm_remove_node(&ggtt->uc_fw); +err_node: drm_mm_remove_node(&ggtt->error_capture); return ret; } @@ -2792,6 +2807,9 @@ void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) if (drm_mm_node_allocated(&ggtt->error_capture)) drm_mm_remove_node(&ggtt->error_capture); + if (drm_mm_node_allocated(&ggtt->uc_fw)) + drm_mm_remove_node(&ggtt->uc_fw); + if (drm_mm_initialized(&ggtt->vm.mm)) { intel_vgt_deballoon(dev_priv); i915_address_space_fini(&ggtt->vm); @@ -3370,7 +3388,8 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) * restriction! */ if (USES_GUC(dev_priv)) { - ggtt->vm.total = min_t(u64, ggtt->vm.total, GUC_GGTT_TOP); + ggtt->vm.total = min_t(u64, ggtt->vm.total, + GUC_GGTT_RESERVED_END); ggtt->mappable_end = min_t(u64, ggtt->mappable_end, ggtt->vm.total); } diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index f597f35b109b..b51e779732c3 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -384,6 +384,7 @@ struct i915_ggtt { u32 pin_bias; struct drm_mm_node error_capture; + struct drm_mm_node uc_fw; }; struct i915_hw_ppgtt { diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index 2c59ff8d9f39..b30cc2642fc4 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -127,6 +127,17 @@ static inline void intel_guc_to_host_event_handler(struct intel_guc *guc) /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */ #define GUC_GGTT_TOP 0xFEE00000 +/* + * This portion of the address space is inaccessible by GuC, + * but still accessible by DMA. We can repurpose this portion + * to house the uC firmware images and perform the image upload. + */ +#define GUC_GGTT_FW_START GUC_GGTT_TOP +#define GUC_GGTT_FW_END 0xFFE00000 +#define GUC_GGTT_RESERVED_END GUC_GGTT_FW_END + +#define GUC_GGTT_FW_SIZE (GUC_GGTT_FW_END - GUC_GGTT_FW_START) + /** * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma * @guc: intel_guc structure.