| Message ID | 20190415142122.533-1-mika.kuoppala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Enable workaround for pixel shader dispatch hang | expand |
Quoting Mika Kuoppala (2019-04-15 15:21:22) > Set chicken bits to workaround a possible pixel shader > dispatch hang. > > Bspec: 14091, ID#0651 > Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > drivers/gpu/drm/i915/intel_workarounds.c | 9 +++++++++ > 2 files changed, 13 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index c1c0f7ab03e9..499cc843443d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8902,11 +8902,15 @@ enum { > #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) > #define DOP_CLOCK_GATING_DISABLE (1 << 0) > #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) > +#define GEN8_DISABLE_RR_ARBITRATION (1 << 1) > #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) > > #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) > #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) > > +#define GEN8_ROW_CHICKEN4 _MMIO(0xe48c) > +#define GEN8_DISABLE_TDL_FIX (1 << 3) > + > #define HALF_SLICE_CHICKEN2 _MMIO(0xe180) > #define GEN8_ST_PO_DISABLE (1 << 13) > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c > index ccaf63679435..4f1a7500ca07 100644 > --- a/drivers/gpu/drm/i915/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > @@ -294,6 +294,15 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine) > FLOW_CONTROL_ENABLE | > PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); > > + /* Bspec wa: 0651, skl G0 onwards */ > + if (!IS_SKL_REVID(i915, SKL_REVID_A0, SKL_REVID_F0)) { IS_SKL_REVID(i915, SKL_REVID_G0, REVID_FOREVER) ? -Chris
On Mon, Apr 15, 2019 at 05:21:22PM +0300, Mika Kuoppala wrote: > Set chicken bits to workaround a possible pixel shader > dispatch hang. > > Bspec: 14091, ID#0651 > Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > drivers/gpu/drm/i915/intel_workarounds.c | 9 +++++++++ > 2 files changed, 13 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index c1c0f7ab03e9..499cc843443d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8902,11 +8902,15 @@ enum { > #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) > #define DOP_CLOCK_GATING_DISABLE (1 << 0) > #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) > +#define GEN8_DISABLE_RR_ARBITRATION (1 << 1) > #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) > > #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) > #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) > > +#define GEN8_ROW_CHICKEN4 _MMIO(0xe48c) > +#define GEN8_DISABLE_TDL_FIX (1 << 3) > + > #define HALF_SLICE_CHICKEN2 _MMIO(0xe180) > #define GEN8_ST_PO_DISABLE (1 << 13) > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c > index ccaf63679435..4f1a7500ca07 100644 > --- a/drivers/gpu/drm/i915/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > @@ -294,6 +294,15 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine) > FLOW_CONTROL_ENABLE | > PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); > > + /* Bspec wa: 0651, skl G0 onwards */ > + if (!IS_SKL_REVID(i915, SKL_REVID_A0, SKL_REVID_F0)) { Aren't all those pre-production? > + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, > + GEN8_DISABLE_RR_ARBITRATION); > + > + /* Make sure the default holds to enable TDL fix */ > + WA_CLR_BIT_MASKED(GEN8_ROW_CHICKEN4, GEN8_DISABLE_TDL_FIX); > + } > + > /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ > if (!IS_COFFEELAKE(i915)) > WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, > -- > 2.17.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoting Ville Syrjälä (2019-04-15 15:25:11) > On Mon, Apr 15, 2019 at 05:21:22PM +0300, Mika Kuoppala wrote: > > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c > > index ccaf63679435..4f1a7500ca07 100644 > > --- a/drivers/gpu/drm/i915/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > > @@ -294,6 +294,15 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine) > > FLOW_CONTROL_ENABLE | > > PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); > > > > + /* Bspec wa: 0651, skl G0 onwards */ > > + if (!IS_SKL_REVID(i915, SKL_REVID_A0, SKL_REVID_F0)) { > > Aren't all those pre-production? intel_detect_preproduction_hw() says yes. -Chris
Chris Wilson <chris@chris-wilson.co.uk> writes: > Quoting Ville Syrjälä (2019-04-15 15:25:11) >> On Mon, Apr 15, 2019 at 05:21:22PM +0300, Mika Kuoppala wrote: >> > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c >> > index ccaf63679435..4f1a7500ca07 100644 >> > --- a/drivers/gpu/drm/i915/intel_workarounds.c >> > +++ b/drivers/gpu/drm/i915/intel_workarounds.c >> > @@ -294,6 +294,15 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine) >> > FLOW_CONTROL_ENABLE | >> > PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); >> > >> > + /* Bspec wa: 0651, skl G0 onwards */ >> > + if (!IS_SKL_REVID(i915, SKL_REVID_A0, SKL_REVID_F0)) { >> >> Aren't all those pre-production? > > intel_detect_preproduction_hw() says yes. v2 coming up. The inverse check got left there as I needed to filter out bxt ones. which turned out to be preprod. The bell should have rung at that point, but didn't. -Mika
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c1c0f7ab03e9..499cc843443d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8902,11 +8902,15 @@ enum { #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) #define DOP_CLOCK_GATING_DISABLE (1 << 0) #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) +#define GEN8_DISABLE_RR_ARBITRATION (1 << 1) #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) +#define GEN8_ROW_CHICKEN4 _MMIO(0xe48c) +#define GEN8_DISABLE_TDL_FIX (1 << 3) + #define HALF_SLICE_CHICKEN2 _MMIO(0xe180) #define GEN8_ST_PO_DISABLE (1 << 13) diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index ccaf63679435..4f1a7500ca07 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -294,6 +294,15 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine) FLOW_CONTROL_ENABLE | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); + /* Bspec wa: 0651, skl G0 onwards */ + if (!IS_SKL_REVID(i915, SKL_REVID_A0, SKL_REVID_F0)) { + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, + GEN8_DISABLE_RR_ARBITRATION); + + /* Make sure the default holds to enable TDL fix */ + WA_CLR_BIT_MASKED(GEN8_ROW_CHICKEN4, GEN8_DISABLE_TDL_FIX); + } + /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ if (!IS_COFFEELAKE(i915)) WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
Set chicken bits to workaround a possible pixel shader dispatch hang. Bspec: 14091, ID#0651 Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_workarounds.c | 9 +++++++++ 2 files changed, 13 insertions(+)