[RFC,5/8] drm/i915: Move all irq related masks to intel_irq

Message ID	20190418205347.6402-6-rodrigo.vivi@intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <intel-gfx-bounces@lists.freedesktop.org> From: Rodrigo Vivi <rodrigo.vivi@intel.com> To: intel-gfx@lists.freedesktop.org Date: Thu, 18 Apr 2019 13:53:44 -0700 Message-Id: <20190418205347.6402-6-rodrigo.vivi@intel.com> In-Reply-To: <20190418205347.6402-1-rodrigo.vivi@intel.com> References: <20190418205347.6402-1-rodrigo.vivi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 5/8] drm/i915: Move all irq related masks to intel_irq Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	Start some re-org around IRQ. \| expand [RFC,0/8] Start some re-org around IRQ. [RFC,1/8] drm/i915: Introduce intel_irq [RFC,2/8] drm/i915: Move IRQ related stuff from intel_rps to the new intel_irq. [RFC,3/8] drm/i915: Move display_irqs_enabled to intel_irq [RFC,4/8] drm/i915: Consolidated iir, imr and ier. [RFC,5/8] drm/i915: Move all irq related masks to intel_irq [RFC,6/8] drm/i915: Prefer passing intel_irq instead of intel_core [RFC,7/8] drm/i915: Start the conversion from passing intel_irq instead of dev_priv/i915 [RFC,8/8] drm/i915: Migrate more gen11 irq functions towards intel_irq and uncore funcs.

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index cb51cf335226..8368daecf478 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -655,6 +655,13 @@ struct intel_irq { u32 pm_iir; u32 pm_imr; u32 pm_ier; + /** Cached value of IMR to avoid reads in updating the bitfield */ + union { + u32 mask; + u32 de_mask[I915_MAX_PIPES]; + }; + u32 gt_mask; + u32 pipestat_mask[I915_MAX_PIPES]; }; struct intel_rps { @@ -1563,15 +1570,8 @@ struct drm_i915_private { /* Sideband mailbox protection */ struct mutex sb_lock; - /** Cached value of IMR to avoid reads in updating the bitfield */ - union { - u32 irq_mask; - u32 de_irq_mask[I915_MAX_PIPES]; - }; - u32 gt_irq_mask; u32 pm_rps_events; u32 pm_guc_events; - u32 pipestat_irq_mask[I915_MAX_PIPES]; struct i915_hotplug hotplug; struct intel_fbc fbc; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 667bbcc01513..0468fbea70af 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -346,13 +346,13 @@ void ilk_update_display_irq(struct drm_i915_private *dev_priv, if (WARN_ON(!intel_irqs_enabled(dev_priv))) return; - new_val = dev_priv->irq_mask; + new_val = dev_priv->irq.mask; new_val &= ~interrupt_mask; new_val |= (~enabled_irq_mask & interrupt_mask); - if (new_val != dev_priv->irq_mask) { - dev_priv->irq_mask = new_val; - I915_WRITE(DEIMR, dev_priv->irq_mask); + if (new_val != dev_priv->irq.mask) { + dev_priv->irq.mask = new_val; + I915_WRITE(DEIMR, dev_priv->irq.mask); POSTING_READ(DEIMR); } } @@ -374,9 +374,9 @@ static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, if (WARN_ON(!intel_irqs_enabled(dev_priv))) return; - dev_priv->gt_irq_mask &= ~interrupt_mask; - dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); - I915_WRITE(GTIMR, dev_priv->gt_irq_mask); + dev_priv->irq.gt_mask &= ~interrupt_mask; + dev_priv->irq.gt_mask |= (~enabled_irq_mask & interrupt_mask); + I915_WRITE(GTIMR, dev_priv->irq.gt_mask); } void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask) @@ -674,13 +674,13 @@ void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, if (WARN_ON(!intel_irqs_enabled(dev_priv))) return; - new_val = dev_priv->de_irq_mask[pipe]; + new_val = dev_priv->irq.de_mask[pipe]; new_val &= ~interrupt_mask; new_val |= (~enabled_irq_mask & interrupt_mask); - if (new_val != dev_priv->de_irq_mask[pipe]) { - dev_priv->de_irq_mask[pipe] = new_val; - I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); + if (new_val != dev_priv->irq.de_mask[pipe]) { + dev_priv->irq.de_mask[pipe] = new_val; + I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->irq.de_mask[pipe]); POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); } } @@ -713,7 +713,7 @@ void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, enum pipe pipe) { - u32 status_mask = dev_priv->pipestat_irq_mask[pipe]; + u32 status_mask = dev_priv->irq.pipestat_mask[pipe]; u32 enable_mask = status_mask << 16; lockdep_assert_held(&dev_priv->irq.lock); @@ -764,10 +764,10 @@ void i915_enable_pipestat(struct drm_i915_private *dev_priv, lockdep_assert_held(&dev_priv->irq.lock); WARN_ON(!intel_irqs_enabled(dev_priv)); - if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask) + if ((dev_priv->irq.pipestat_mask[pipe] & status_mask) == status_mask) return; - dev_priv->pipestat_irq_mask[pipe] |= status_mask; + dev_priv->irq.pipestat_mask[pipe] |= status_mask; enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); I915_WRITE(reg, enable_mask | status_mask); @@ -787,10 +787,10 @@ void i915_disable_pipestat(struct drm_i915_private *dev_priv, lockdep_assert_held(&dev_priv->irq.lock); WARN_ON(!intel_irqs_enabled(dev_priv)); - if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0) + if ((dev_priv->irq.pipestat_mask[pipe] & status_mask) == 0) return; - dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; + dev_priv->irq.pipestat_mask[pipe] &= ~status_mask; enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); I915_WRITE(reg, enable_mask | status_mask); @@ -1901,7 +1901,7 @@ static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv) PIPESTAT_INT_STATUS_MASK | PIPE_FIFO_UNDERRUN_STATUS); - dev_priv->pipestat_irq_mask[pipe] = 0; + dev_priv->irq.pipestat_mask[pipe] = 0; } } @@ -1944,7 +1944,7 @@ static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, break; } if (iir & iir_bit) - status_mask |= dev_priv->pipestat_irq_mask[pipe]; + status_mask |= dev_priv->irq.pipestat_mask[pipe]; if (!status_mask) continue; @@ -3423,7 +3423,7 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) i9xx_pipestat_irq_reset(dev_priv); GEN3_IRQ_RESET(uncore, VLV_); - dev_priv->irq_mask = ~0u; + dev_priv->irq.mask = ~0u; } static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) @@ -3450,11 +3450,11 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | I915_LPE_PIPE_C_INTERRUPT; - WARN_ON(dev_priv->irq_mask != ~0u); + WARN_ON(dev_priv->irq.mask != ~0u); - dev_priv->irq_mask = ~enable_mask; + dev_priv->irq.mask = ~enable_mask; - GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask); + GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq.mask, enable_mask); } /* drm_dma.h hooks @@ -3593,8 +3593,8 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, for_each_pipe_masked(dev_priv, pipe, pipe_mask) GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, - dev_priv->de_irq_mask[pipe], - ~dev_priv->de_irq_mask[pipe] | extra_ier); + dev_priv->irq.de_mask[pipe], + ~dev_priv->irq.de_mask[pipe] | extra_ier); spin_unlock_irq(&dev_priv->irq.lock); } @@ -3921,10 +3921,10 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) pm_irqs = gt_irqs = 0; - dev_priv->gt_irq_mask = ~0; + dev_priv->irq.gt_mask = ~0; if (HAS_L3_DPF(dev_priv)) { /* L3 parity interrupt is always unmasked. */ - dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv); + dev_priv->irq.gt_mask = ~GT_PARITY_ERROR(dev_priv); gt_irqs |= GT_PARITY_ERROR(dev_priv); } @@ -3935,7 +3935,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; } - GEN3_IRQ_INIT(uncore, GT, dev_priv->gt_irq_mask, gt_irqs); + GEN3_IRQ_INIT(uncore, GT, dev_priv->irq.gt_mask, gt_irqs); if (INTEL_GEN(dev_priv) >= 6) { /* @@ -3979,11 +3979,11 @@ static int ironlake_irq_postinstall(struct drm_device *dev) display_mask |= DE_EDP_PSR_INT_HSW; } - dev_priv->irq_mask = ~display_mask; + dev_priv->irq.mask = ~display_mask; ibx_irq_pre_postinstall(dev); - GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask, + GEN3_IRQ_INIT(uncore, DE, dev_priv->irq.mask, display_mask | extra_mask); gen5_gt_irq_postinstall(dev); @@ -4129,12 +4129,12 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) intel_psr_irq_control(dev_priv, dev_priv->psr.debug); for_each_pipe(dev_priv, pipe) { - dev_priv->de_irq_mask[pipe] = ~de_pipe_masked; + dev_priv->irq.de_mask[pipe] = ~de_pipe_masked; if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, - dev_priv->de_irq_mask[pipe], + dev_priv->irq.de_mask[pipe], de_pipe_enables); } @@ -4275,7 +4275,7 @@ static int i8xx_irq_postinstall(struct drm_device *dev) I915_ERROR_MEMORY_REFRESH)); /* Unmask the interrupts that we always want on. */ - dev_priv->irq_mask = + dev_priv->irq.mask = ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | I915_MASTER_ERROR_INTERRUPT); @@ -4286,7 +4286,7 @@ static int i8xx_irq_postinstall(struct drm_device *dev) I915_MASTER_ERROR_INTERRUPT | I915_USER_INTERRUPT; - GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask); + GEN2_IRQ_INIT(uncore, dev_priv->irq.mask, enable_mask); /* Interrupt setup is already guaranteed to be single-threaded, this is * just to make the assert_spin_locked check happy. */ @@ -4444,7 +4444,7 @@ static int i915_irq_postinstall(struct drm_device *dev) I915_ERROR_MEMORY_REFRESH)); /* Unmask the interrupts that we always want on. */ - dev_priv->irq_mask = + dev_priv->irq.mask = ~(I915_ASLE_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | @@ -4461,10 +4461,10 @@ static int i915_irq_postinstall(struct drm_device *dev) /* Enable in IER... */ enable_mask |= I915_DISPLAY_PORT_INTERRUPT; /* and unmask in IMR */ - dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; + dev_priv->irq.mask &= ~I915_DISPLAY_PORT_INTERRUPT; } - GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); + GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq.mask, enable_mask); /* Interrupt setup is already guaranteed to be single-threaded, this is * just to make the assert_spin_locked check happy. */ @@ -4568,7 +4568,7 @@ static int i965_irq_postinstall(struct drm_device *dev) I915_WRITE(EMR, error_mask); /* Unmask the interrupts that we always want on. */ - dev_priv->irq_mask = + dev_priv->irq.mask = ~(I915_ASLE_INTERRUPT | I915_DISPLAY_PORT_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | @@ -4586,7 +4586,7 @@ static int i965_irq_postinstall(struct drm_device *dev) if (IS_G4X(dev_priv)) enable_mask |= I915_BSD_USER_INTERRUPT; - GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); + GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq.mask, enable_mask); /* Interrupt setup is already guaranteed to be single-threaded, this is * just to make the assert_spin_locked check happy. */ diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 3844581f622c..db966d9106dc 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -970,16 +970,16 @@ gen5_irq_disable(struct intel_engine_cs *engine) static void i9xx_irq_enable(struct intel_engine_cs *engine) { - engine->i915->irq_mask &= ~engine->irq_enable_mask; - intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); + engine->i915->irq.mask &= ~engine->irq_enable_mask; + intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq.mask); intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR); } static void i9xx_irq_disable(struct intel_engine_cs *engine) { - engine->i915->irq_mask |= engine->irq_enable_mask; - intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); + engine->i915->irq.mask |= engine->irq_enable_mask; + intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq.mask); } static void @@ -987,8 +987,8 @@ i8xx_irq_enable(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; - dev_priv->irq_mask &= ~engine->irq_enable_mask; - I915_WRITE16(GEN2_IMR, dev_priv->irq_mask); + dev_priv->irq.mask &= ~engine->irq_enable_mask; + I915_WRITE16(GEN2_IMR, dev_priv->irq.mask); POSTING_READ16(RING_IMR(engine->mmio_base)); } @@ -997,8 +997,8 @@ i8xx_irq_disable(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; - dev_priv->irq_mask |= engine->irq_enable_mask; - I915_WRITE16(GEN2_IMR, dev_priv->irq_mask); + dev_priv->irq.mask |= engine->irq_enable_mask; + I915_WRITE16(GEN2_IMR, dev_priv->irq.mask); } static int

[RFC,5/8] drm/i915: Move all irq related masks to intel_irq

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