| Message ID | 20190503193143.28240-1-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] drm/i915: Replace intel_ddi_pll_init() | expand |
On Fri, May 03, 2019 at 10:31:42PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > intel_ddi_pll_init() is an anachronism. Rename it to > hsw_assert_cdclk() and move it to the power domain init code. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Ok, makes sense to check this during system resume too: Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 25 ------------------------- > drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++++++++++++++++++++- > 2 files changed, 21 insertions(+), 26 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c > index bb81f3506222..bf5e2541c35e 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > @@ -1881,27 +1881,6 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = { > .get_hw_state = bxt_ddi_pll_get_hw_state, > }; > > -static void intel_ddi_pll_init(struct drm_device *dev) > -{ > - struct drm_i915_private *dev_priv = to_i915(dev); > - > - if (INTEL_GEN(dev_priv) < 9) { > - u32 val = I915_READ(LCPLL_CTL); > - > - /* > - * The LCPLL register should be turned on by the BIOS. For now > - * let's just check its state and print errors in case > - * something is wrong. Don't even try to turn it on. > - */ > - > - if (val & LCPLL_CD_SOURCE_FCLK) > - DRM_ERROR("CDCLK source is not LCPLL\n"); > - > - if (val & LCPLL_PLL_DISABLE) > - DRM_ERROR("LCPLL is disabled\n"); > - } > -} > - > struct intel_dpll_mgr { > const struct dpll_info *dpll_info; > > @@ -3305,10 +3284,6 @@ void intel_shared_dpll_init(struct drm_device *dev) > mutex_init(&dev_priv->dpll_lock); > > BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); > - > - /* FIXME: Move this to a more suitable place */ > - if (HAS_DDI(dev_priv)) > - intel_ddi_pll_init(dev); > } > > /** > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 1b7ea6bab613..b1fd2ae99199 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -3625,6 +3625,23 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) > I915_WRITE(MBUS_ABOX_CTL, val); > } > > +static void hsw_assert_cdclk(struct drm_i915_private *dev_priv) > +{ > + u32 val = I915_READ(LCPLL_CTL); > + > + /* > + * The LCPLL register should be turned on by the BIOS. For now > + * let's just check its state and print errors in case > + * something is wrong. Don't even try to turn it on. > + */ > + > + if (val & LCPLL_CD_SOURCE_FCLK) > + DRM_ERROR("CDCLK source is not LCPLL\n"); > + > + if (val & LCPLL_PLL_DISABLE) > + DRM_ERROR("LCPLL is disabled\n"); > +} > + > static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv, > bool enable) > { > @@ -4085,7 +4102,10 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume) > mutex_unlock(&power_domains->lock); > assert_ved_power_gated(i915); > assert_isp_power_gated(i915); > - } else if (IS_IVYBRIDGE(i915) || INTEL_GEN(i915) >= 7) { > + } else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) { > + hsw_assert_cdclk(i915); > + intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915)); > + } else if (IS_IVYBRIDGE(i915)) { > intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915)); > } > > -- > 2.21.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index bb81f3506222..bf5e2541c35e 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -1881,27 +1881,6 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = { .get_hw_state = bxt_ddi_pll_get_hw_state, }; -static void intel_ddi_pll_init(struct drm_device *dev) -{ - struct drm_i915_private *dev_priv = to_i915(dev); - - if (INTEL_GEN(dev_priv) < 9) { - u32 val = I915_READ(LCPLL_CTL); - - /* - * The LCPLL register should be turned on by the BIOS. For now - * let's just check its state and print errors in case - * something is wrong. Don't even try to turn it on. - */ - - if (val & LCPLL_CD_SOURCE_FCLK) - DRM_ERROR("CDCLK source is not LCPLL\n"); - - if (val & LCPLL_PLL_DISABLE) - DRM_ERROR("LCPLL is disabled\n"); - } -} - struct intel_dpll_mgr { const struct dpll_info *dpll_info; @@ -3305,10 +3284,6 @@ void intel_shared_dpll_init(struct drm_device *dev) mutex_init(&dev_priv->dpll_lock); BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); - - /* FIXME: Move this to a more suitable place */ - if (HAS_DDI(dev_priv)) - intel_ddi_pll_init(dev); } /** diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 1b7ea6bab613..b1fd2ae99199 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -3625,6 +3625,23 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) I915_WRITE(MBUS_ABOX_CTL, val); } +static void hsw_assert_cdclk(struct drm_i915_private *dev_priv) +{ + u32 val = I915_READ(LCPLL_CTL); + + /* + * The LCPLL register should be turned on by the BIOS. For now + * let's just check its state and print errors in case + * something is wrong. Don't even try to turn it on. + */ + + if (val & LCPLL_CD_SOURCE_FCLK) + DRM_ERROR("CDCLK source is not LCPLL\n"); + + if (val & LCPLL_PLL_DISABLE) + DRM_ERROR("LCPLL is disabled\n"); +} + static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv, bool enable) { @@ -4085,7 +4102,10 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume) mutex_unlock(&power_domains->lock); assert_ved_power_gated(i915); assert_isp_power_gated(i915); - } else if (IS_IVYBRIDGE(i915) || INTEL_GEN(i915) >= 7) { + } else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) { + hsw_assert_cdclk(i915); + intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915)); + } else if (IS_IVYBRIDGE(i915)) { intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915)); }