From patchwork Wed May 8 12:10:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10935587 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5FF3114B6 for ; Wed, 8 May 2019 12:11:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4EE2F289B0 for ; Wed, 8 May 2019 12:11:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 437E5289C0; Wed, 8 May 2019 12:11:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C7458289B0 for ; Wed, 8 May 2019 12:11:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1087989949; Wed, 8 May 2019 12:11:28 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id C8B6C898BC; Wed, 8 May 2019 12:11:24 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 May 2019 05:11:24 -0700 X-ExtLoop1: 1 Received: from jzapadkx-mobl1.ger.corp.intel.com (HELO localhost.localdomain) ([10.252.0.159]) by fmsmga008.fm.intel.com with ESMTP; 08 May 2019 05:11:23 -0700 From: Tvrtko Ursulin To: igt-dev@lists.freedesktop.org Date: Wed, 8 May 2019 13:10:56 +0100 Message-Id: <20190508121058.27038-20-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190508121058.27038-1-tvrtko.ursulin@linux.intel.com> References: <20190508121058.27038-1-tvrtko.ursulin@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t 19/21] gem_wsim: Per context SSEU control X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin A new workload command ('S') is added which allows per context slice (re-)configuration. Signed-off-by: Tvrtko Ursulin --- benchmarks/gem_wsim.c | 69 +++++++++++++++++++++++++++++++++++------- benchmarks/wsim/README | 23 +++++++++++++- 2 files changed, 80 insertions(+), 12 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 64dd251a25eb..ed5acee02e20 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -87,6 +87,7 @@ enum w_type LOAD_BALANCE, BOND, TERMINATE, + SSEU }; struct deps @@ -136,6 +137,7 @@ struct w_step uint64_t bond_mask; enum intel_engine_id bond_master; }; + int sseu; }; /* Implementation details */ @@ -171,6 +173,7 @@ struct ctx { bool targets_instance; bool wants_balance; unsigned int static_vcs; + uint64_t sseu; }; struct workload @@ -241,6 +244,7 @@ static unsigned int context_vcs_rr; static int verbose = 1; static int fd; +static struct drm_i915_gem_context_param_sseu device_sseu; #define SWAPVCS (1<<0) #define SEQNO (1<<1) @@ -456,6 +460,27 @@ parse_workload(struct w_arg *arg, unsigned int flags, struct workload *app_w) int_field(SYNC, target, tmp >= 0 || ((int)nr_steps + tmp) < 0, "Invalid sync target at step %u!\n"); + } else if (!strcmp(field, "S")) { + unsigned int nr = 0; + while ((field = strtok_r(fstart, ".", &fctx))) { + tmp = atoi(field); + check_arg(tmp <= 0 && nr == 0, + "Invalid context at step %u!\n", + nr_steps); + check_arg(nr > 1, + "Invalid SSEU format at step %u!\n", + nr_steps); + + if (nr == 0) + step.context = tmp; + else if (nr == 1) + step.sseu = tmp; + + nr++; + } + + step.type = SSEU; + goto add_step; } else if (!strcmp(field, "t")) { int_field(THROTTLE, throttle, tmp < 0, @@ -1071,24 +1096,24 @@ static void __ctx_set_prio(uint32_t ctx_id, unsigned int prio) gem_context_set_param(fd, ¶m); } -static void -set_ctx_sseu(uint32_t ctx) +static uint64_t +set_ctx_sseu(uint32_t ctx, uint64_t slice_mask) { - struct drm_i915_gem_context_param_sseu sseu = { }; + struct drm_i915_gem_context_param_sseu sseu = device_sseu; struct drm_i915_gem_context_param param = { }; - sseu.class = I915_ENGINE_CLASS_RENDER; - sseu.instance = 0; + if (slice_mask == -1) + slice_mask = device_sseu.slice_mask; + + sseu.slice_mask = slice_mask; param.ctx_id = ctx; param.param = I915_CONTEXT_PARAM_SSEU; param.value = (uintptr_t)&sseu; - gem_context_get_param(fd, ¶m); - - sseu.slice_mask = 1; - gem_context_set_param(fd, ¶m); + + return slice_mask; } static int @@ -1287,6 +1312,7 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) igt_assert(ctx_id); ctx->id = ctx_id; + ctx->sseu = device_sseu.slice_mask; if (flags & GLOBAL_BALANCE) { ctx->static_vcs = context_vcs_rr; @@ -1439,8 +1465,10 @@ prepare_workload(unsigned int id, struct workload *wrk, unsigned int flags) gem_context_set_param(fd, ¶m); } - if (wrk->sseu) - set_ctx_sseu(arg.ctx_id); + if (wrk->sseu) { + /* Set to slice 0 only, one slice. */ + ctx->sseu = set_ctx_sseu(ctx_id, 1); + } } /* Record default preemption. */ @@ -2409,6 +2437,13 @@ static void *run_workload(void *data) w->type == LOAD_BALANCE || w->type == BOND) { continue; + } else if (w->type == SSEU) { + if (w->sseu != wrk->ctx_list[w->context].sseu) { + wrk->ctx_list[w->context].sseu = + set_ctx_sseu(wrk->ctx_list[w->context].id, + w->sseu); + } + continue; } if (do_sleep || w->type == PERIOD) { @@ -2725,6 +2760,16 @@ static void init_clocks(void) rcs_end - rcs_start, 1e6*t, 1024e6 * t / (rcs_end - rcs_start)); } +static void get_device_sseu(void) +{ + struct drm_i915_gem_context_param param = { }; + + param.param = I915_CONTEXT_PARAM_SSEU; + param.value = (uintptr_t)&device_sseu; + + gem_context_get_param(fd, ¶m); +} + int main(int argc, char **argv) { unsigned int repeat = 1; @@ -2753,6 +2798,8 @@ int main(int argc, char **argv) fd = __drm_open_driver(DRIVER_INTEL); igt_require(fd); + get_device_sseu(); + init_clocks(); while ((c = getopt(argc, argv, diff --git a/benchmarks/wsim/README b/benchmarks/wsim/README index c94d01018419..d7c255b9527c 100644 --- a/benchmarks/wsim/README +++ b/benchmarks/wsim/README @@ -5,7 +5,7 @@ ctx.engine.duration_us.dependency.wait,... ..[-]|*.[/][...].<0|1>,... B. M..[|]... -P|X.. +P|S|X.. d|p|s|t|q|a|T.,... b... f @@ -30,6 +30,7 @@ Additional workload steps are also supported: 'b' - Set up engine bonds. 'M' - Set up engine map. 'P' - Context priority. + 'S' - Context SSEU configuration. 'T' - Terminate an infinite batch. 'X' - Context preemption control. @@ -249,3 +250,23 @@ then look like: 1.DEFAULT.1000.f-1.0 2.DEFAULT.1000.s-1.0 a.-3 + +Context SSEU configuration +-------------------------- + + S.1.1 + 1.RCS.1000.0.0 + S.2.-1 + 2.RCS.1000.0.0 + +Context 1 is configured to run with one enabled slice (slice mask 1) and a batch +is sumitted against it. Context 2 is configured to run with all slices (this is +the default so the command could also be omitted) and a batch submitted against +it. + +This shows the dynamic SSEU reconfiguration cost beween two contexts competing +for the render engine. + +Slice mask of -1 has a special meaning of "all slices". Otherwise any integer +can be specifying as the slice mask, but beware any apart from 1 and -1 can make +the workload not portable between different GPUs.