From patchwork Tue May 14 16:46:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Summers, Stuart" X-Patchwork-Id: 10943403 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DC204112C for ; Tue, 14 May 2019 16:46:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA476287EF for ; Tue, 14 May 2019 16:46:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BE6E72880D; Tue, 14 May 2019 16:46:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7394F287EF for ; Tue, 14 May 2019 16:46:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7DB7E89293; Tue, 14 May 2019 16:46:55 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 82ED489293 for ; Tue, 14 May 2019 16:46:54 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 May 2019 09:46:53 -0700 X-ExtLoop1: 1 Received: from jssummer-desk.ra.intel.com ([10.54.134.159]) by orsmga003.jf.intel.com with ESMTP; 14 May 2019 09:46:53 -0700 From: Stuart Summers To: intel-gfx@lists.freedesktop.org Date: Tue, 14 May 2019 09:46:53 -0700 Message-Id: <20190514164653.935-2-stuart.summers@intel.com> X-Mailer: git-send-email 2.21.0.5.gaeb582a983 In-Reply-To: <20190514164653.935-1-stuart.summers@intel.com> References: <20190514164653.935-1-stuart.summers@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Extend reset modparam to domain resets X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP In the event a platform does not properly implement reset, do not go through reset flows for engine domains to avoid an unlikely situation where writes are accepted but register values are never cleared, as this can result in GPU wedges in these cases. Signed-off-by: Stuart Summers --- drivers/gpu/drm/i915/gt/intel_reset.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 464369bc55ad..81f9f9f73b1c 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -309,6 +309,12 @@ static int gen6_hw_domain_reset(struct drm_i915_private *i915, struct intel_uncore *uncore = &i915->uncore; int err; + if (!i915_modparams.reset) { + DRM_DEBUG_DRIVER("Skipping 0x%08x engines reset\n", + hw_domain_mask); + return 0; + } + /* * GEN6_GDRST is not in the gt power well, no need to check * for fifo space for the write or forcewake the chip for @@ -517,6 +523,13 @@ static int gen8_engine_reset_prepare(struct intel_engine_cs *engine) return 0; } + if (!i915_modparams.reset) { + DRM_DEBUG_DRIVER("Skipping %s reset request {request: %08x, RESET_CTL: %08x}\n", + engine->name, request, + intel_uncore_read_fw(uncore, reg)); + return 0; + } + intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request)); ret = __intel_wait_for_register_fw(uncore, reg, mask, ack, 700, 0, NULL);