From patchwork Thu Jun 6 00:23:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Kasireddy, Vivek" X-Patchwork-Id: 10978147 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A5B2714E5 for ; Thu, 6 Jun 2019 00:24:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8BBFB28449 for ; Thu, 6 Jun 2019 00:24:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7FC922846C; Thu, 6 Jun 2019 00:24:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CA9BA28449 for ; Thu, 6 Jun 2019 00:24:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9C2DE895C4; Thu, 6 Jun 2019 00:24:25 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 755EC895C4 for ; Thu, 6 Jun 2019 00:24:24 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Jun 2019 17:24:23 -0700 X-ExtLoop1: 1 Received: from orsmsx104.amr.corp.intel.com ([10.22.225.131]) by orsmga006.jf.intel.com with ESMTP; 05 Jun 2019 17:24:23 -0700 Received: from orsmsx151.amr.corp.intel.com (10.22.226.38) by ORSMSX104.amr.corp.intel.com (10.22.225.131) with Microsoft SMTP Server (TLS) id 14.3.408.0; Wed, 5 Jun 2019 17:24:23 -0700 Received: from vkasired-desk2.fm.intel.com (10.22.254.140) by ORSMSX151.amr.corp.intel.com (10.22.226.38) with Microsoft SMTP Server (TLS) id 14.3.408.0; Wed, 5 Jun 2019 17:24:23 -0700 From: Vivek Kasireddy To: Date: Wed, 5 Jun 2019 17:23:54 -0700 Message-ID: <20190606002354.26660-1-vivek.kasireddy@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190605190556.10842.99420@emeril.freedesktop.org> References: <20190605190556.10842.99420@emeril.freedesktop.org> MIME-Version: 1.0 X-Originating-IP: [10.22.254.140] Subject: [Intel-gfx] [PATCH] drm/i915/ehl: Add support for DPLL4 (v6) X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support for DPLL4 on EHL that include the following restrictions: - DPLL4 cannot be used with DDIA (combo port A internal eDP usage). DPLL4 can be used with other DDIs, including DDID (combo port A external usage). - DPLL4 cannot be enabled when DC5 or DC6 are enabled. - The DPLL4 enable, lock, power enabled, and power state are connected to the MGPLL1_ENABLE register. v2: (suggestions from Bob Paauwe) - Rework ehl_get_dpll() function to call intel_find_shared_dpll() and iterate twice: once for Combo plls and once for MG plls. - Use MG pll funcs for DPLL4 instead of creating new ones and modify mg_pll_enable to include the restrictions for EHL. v3: Fix compilation error v4: (suggestions from Lucas and Ville) - Treat DPLL4 as a combo phy PLL and not as MG PLL - Disable DC states when this DPLL is being enabled - Reuse icl_get_dpll instead of creating a separate one for EHL v5: (suggestion from Ville) - Refcount the DC OFF power domains during the enabling and disabling of this DPLL. v6: rebase Cc: Lucas De Marchi Cc: José Roberto de Souza Cc: Ville Syrjälä Cc: Matt Roper Signed-off-by: Vivek Kasireddy --- drivers/gpu/drm/i915/intel_display_power.c | 20 +++++++++++ drivers/gpu/drm/i915/intel_display_power.h | 6 ++++ drivers/gpu/drm/i915/intel_dpll_mgr.c | 40 +++++++++++++++++++--- drivers/gpu/drm/i915/intel_dpll_mgr.h | 5 +++ 4 files changed, 67 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display_power.c b/drivers/gpu/drm/i915/intel_display_power.c index 278a7edc94f5..fd6d0d6a285a 100644 --- a/drivers/gpu/drm/i915/intel_display_power.c +++ b/drivers/gpu/drm/i915/intel_display_power.c @@ -4524,6 +4524,26 @@ void intel_power_domains_resume(struct drm_i915_private *i915) intel_power_domains_verify_state(i915); } +void icl_disable_dc_states(struct drm_i915_private *dev_priv, + struct intel_shared_dpll *pll) +{ + enum intel_display_power_domain domain; + + for_each_power_domain(domain, ICL_DISPLAY_DC_OFF_POWER_DOMAINS) + pll->wakerefs[domain] = intel_display_power_get(dev_priv, + domain); +} + +void icl_enable_dc_states(struct drm_i915_private *dev_priv, + struct intel_shared_dpll *pll) +{ + enum intel_display_power_domain domain; + + for_each_power_domain(domain, ICL_DISPLAY_DC_OFF_POWER_DOMAINS) + intel_display_power_put(dev_priv, domain, + pll->wakerefs[domain]); +} + #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) static void intel_power_domains_dump_info(struct drm_i915_private *i915) diff --git a/drivers/gpu/drm/i915/intel_display_power.h b/drivers/gpu/drm/i915/intel_display_power.h index ff57b0a7fe59..2abaa3806ec6 100644 --- a/drivers/gpu/drm/i915/intel_display_power.h +++ b/drivers/gpu/drm/i915/intel_display_power.h @@ -12,6 +12,7 @@ struct drm_i915_private; struct intel_encoder; +struct intel_shared_dpll; enum intel_display_power_domain { POWER_DOMAIN_DISPLAY_CORE, @@ -285,4 +286,9 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder, bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, enum dpio_channel ch, bool override); +void icl_disable_dc_states(struct drm_i915_private *dev_priv, + struct intel_shared_dpll *pll); +void icl_enable_dc_states(struct drm_i915_private *dev_priv, + struct intel_shared_dpll *pll); + #endif /* __INTEL_DISPLAY_POWER_H__ */ diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 69787f259677..2829b37e2909 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -22,8 +22,8 @@ */ #include "intel_dpio_phy.h" -#include "intel_dpll_mgr.h" #include "intel_drv.h" +#include "intel_dpll_mgr.h" /** * DOC: Display PLLs @@ -2806,6 +2806,12 @@ icl_get_dpll(struct intel_crtc_state *crtc_state, if (intel_port_is_combophy(dev_priv, port)) { min = DPLL_ID_ICL_DPLL0; max = DPLL_ID_ICL_DPLL1; + + if (IS_ELKHARTLAKE(dev_priv)) { + if (encoder->type != INTEL_OUTPUT_EDP) + max = DPLL_ID_EHL_DPLL4; + } + ret = icl_calc_dpll_state(crtc_state, encoder); } else if (intel_port_is_tc(dev_priv, port)) { if (encoder->type == INTEL_OUTPUT_DP_MST) { @@ -2945,8 +2951,14 @@ static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state) { - return icl_pll_get_hw_state(dev_priv, pll, hw_state, - CNL_DPLL_ENABLE(pll->info->id)); + i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); + + if (IS_ELKHARTLAKE(dev_priv) && + pll->info->id == DPLL_ID_EHL_DPLL4) { + enable_reg = MG_PLL_ENABLE(0); + } + + return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg); } static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv, @@ -3057,6 +3069,14 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv, { i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); + if (IS_ELKHARTLAKE(dev_priv) && + pll->info->id == DPLL_ID_EHL_DPLL4) { + enable_reg = MG_PLL_ENABLE(0); + + /* Need to disable DC states when this DPLL is enabled. */ + icl_disable_dc_states(dev_priv, pll); + } + icl_pll_power_enable(dev_priv, pll, enable_reg); icl_dpll_write(dev_priv, pll); @@ -3152,7 +3172,18 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv, static void combo_pll_disable(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) { - icl_pll_disable(dev_priv, pll, CNL_DPLL_ENABLE(pll->info->id)); + i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); + + if (IS_ELKHARTLAKE(dev_priv) && + pll->info->id == DPLL_ID_EHL_DPLL4) { + enable_reg = MG_PLL_ENABLE(0); + icl_pll_disable(dev_priv, pll, enable_reg); + + icl_enable_dc_states(dev_priv, pll); + return; + } + + icl_pll_disable(dev_priv, pll, enable_reg); } static void tbt_pll_disable(struct drm_i915_private *dev_priv, @@ -3230,6 +3261,7 @@ static const struct intel_dpll_mgr icl_pll_mgr = { static const struct dpll_info ehl_plls[] = { { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 }, { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 }, + { "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 }, { }, }; diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h index b5dd9c7ad772..cf05e53b3a12 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h @@ -117,6 +117,10 @@ enum intel_dpll_id { * @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1 */ DPLL_ID_ICL_DPLL1 = 1, + /** + * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4 + */ + DPLL_ID_EHL_DPLL4 = 2, /** * @DPLL_ID_ICL_TBTPLL: ICL TBT PLL */ @@ -312,6 +316,7 @@ struct intel_shared_dpll { * @info: platform specific info */ const struct dpll_info *info; + intel_wakeref_t wakerefs[POWER_DOMAIN_NUM]; }; #define SKL_DPLL0 0