diff mbox series

[17/21] drm/i915: Consolidate some open coded mmio rmw

Message ID 20190606093639.9372-18-tvrtko.ursulin@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series Implicit dev_priv removal | expand

Commit Message

Tvrtko Ursulin June 6, 2019, 9:36 a.m. UTC 
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Replace some gen6/7 open coded rmw with intel_uncore_rmw.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 42 +++++++++++++----------------
 1 file changed, 18 insertions(+), 24 deletions(-)

Comments

Rodrigo Vivi June 6, 2019, 1:46 p.m. UTC | #1 
On Thu, Jun 06, 2019 at 10:36:35AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Replace some gen6/7 open coded rmw with intel_uncore_rmw.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 42 +++++++++++++----------------
>  1 file changed, 18 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index b2c2dc99bf8a..fe9cd4ea9671 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1697,13 +1697,10 @@ static void gen7_ppgtt_enable(struct intel_uncore *uncore)
>  {
>  	struct drm_i915_private *i915 = uncore_to_i915(uncore);
>  	struct intel_engine_cs *engine;
> -	u32 ecochk, ecobits;
>  	enum intel_engine_id id;
> +	u32 ecochk;
>  
> -	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
> -	intel_uncore_write(uncore,
> -			   GAC_ECO_BITS,
> -			   ecobits | ECOBITS_PPGTT_CACHE64B);
> +	intel_uncore_rmw(uncore, GAC_ECO_BITS, 0, ECOBITS_PPGTT_CACHE64B);
>  
>  	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
>  	if (IS_HASWELL(i915)) {
> @@ -1724,22 +1721,20 @@ static void gen7_ppgtt_enable(struct intel_uncore *uncore)
>  
>  static void gen6_ppgtt_enable(struct intel_uncore *uncore)
>  {
> -	u32 ecochk, gab_ctl, ecobits;
> +	intel_uncore_rmw(uncore,
> +			 GAC_ECO_BITS,
> +			 0,
> +			 ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
>  
> -	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
> -	intel_uncore_write(uncore,
> -			   GAC_ECO_BITS,
> -			   ecobits | ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
> +	intel_uncore_rmw(uncore,
> +			 GAB_CTL,
> +			 0,
> +			 GAB_CTL_CONT_AFTER_PAGEFAULT);
>  
> -	gab_ctl = intel_uncore_read(uncore, GAB_CTL);
> -	intel_uncore_write(uncore,
> -			   GAB_CTL,
> -			   gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
> -
> -	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
> -	intel_uncore_write(uncore,
> -			   GAM_ECOCHK,
> -			   ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
> +	intel_uncore_rmw(uncore,
> +			 GAM_ECOCHK,
> +			 0,
> +			 ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
>  
>  	if (HAS_PPGTT(uncore_to_i915(uncore))) /* may be disabled for VT-d */
>  		intel_uncore_write(uncore,
> @@ -2234,11 +2229,10 @@ static void gtt_write_workarounds(struct intel_uncore *uncore)
>  	 */
>  	if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
>  	    INTEL_GEN(i915) <= 10)
> -		intel_uncore_write(uncore,
> -				   GEN8_GAMW_ECO_DEV_RW_IA,
> -				   intel_uncore_read(uncore,
> -						     GEN8_GAMW_ECO_DEV_RW_IA) |
> -				   GAMW_ECO_ENABLE_64K_IPS_FIELD);
> +		intel_uncore_rmw(uncore,
> +				 GEN8_GAMW_ECO_DEV_RW_IA,
> +				 0,
> +				 GAMW_ECO_ENABLE_64K_IPS_FIELD);
>  }
>  
>  int i915_ppgtt_init_hw(struct intel_uncore *uncore)
> -- 
> 2.20.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index b2c2dc99bf8a..fe9cd4ea9671 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1697,13 +1697,10 @@  static void gen7_ppgtt_enable(struct intel_uncore *uncore)
 {
 	struct drm_i915_private *i915 = uncore_to_i915(uncore);
 	struct intel_engine_cs *engine;
-	u32 ecochk, ecobits;
 	enum intel_engine_id id;
+	u32 ecochk;
 
-	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
-	intel_uncore_write(uncore,
-			   GAC_ECO_BITS,
-			   ecobits | ECOBITS_PPGTT_CACHE64B);
+	intel_uncore_rmw(uncore, GAC_ECO_BITS, 0, ECOBITS_PPGTT_CACHE64B);
 
 	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
 	if (IS_HASWELL(i915)) {
@@ -1724,22 +1721,20 @@  static void gen7_ppgtt_enable(struct intel_uncore *uncore)
 
 static void gen6_ppgtt_enable(struct intel_uncore *uncore)
 {
-	u32 ecochk, gab_ctl, ecobits;
+	intel_uncore_rmw(uncore,
+			 GAC_ECO_BITS,
+			 0,
+			 ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
 
-	ecobits = intel_uncore_read(uncore, GAC_ECO_BITS);
-	intel_uncore_write(uncore,
-			   GAC_ECO_BITS,
-			   ecobits | ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
+	intel_uncore_rmw(uncore,
+			 GAB_CTL,
+			 0,
+			 GAB_CTL_CONT_AFTER_PAGEFAULT);
 
-	gab_ctl = intel_uncore_read(uncore, GAB_CTL);
-	intel_uncore_write(uncore,
-			   GAB_CTL,
-			   gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
-
-	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
-	intel_uncore_write(uncore,
-			   GAM_ECOCHK,
-			   ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
+	intel_uncore_rmw(uncore,
+			 GAM_ECOCHK,
+			 0,
+			 ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
 
 	if (HAS_PPGTT(uncore_to_i915(uncore))) /* may be disabled for VT-d */
 		intel_uncore_write(uncore,
@@ -2234,11 +2229,10 @@  static void gtt_write_workarounds(struct intel_uncore *uncore)
 	 */
 	if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
 	    INTEL_GEN(i915) <= 10)
-		intel_uncore_write(uncore,
-				   GEN8_GAMW_ECO_DEV_RW_IA,
-				   intel_uncore_read(uncore,
-						     GEN8_GAMW_ECO_DEV_RW_IA) |
-				   GAMW_ECO_ENABLE_64K_IPS_FIELD);
+		intel_uncore_rmw(uncore,
+				 GEN8_GAMW_ECO_DEV_RW_IA,
+				 0,
+				 GAMW_ECO_ENABLE_64K_IPS_FIELD);
 }
 
 int i915_ppgtt_init_hw(struct intel_uncore *uncore)