| Message ID | 20190619230222.4346-4-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v6,1/4] drm/i915/bdw+: Move misc display IRQ handling to it own function | expand |
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index ed422b788d88..da56b8b1b9b9 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -545,6 +545,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, if (!dev_priv->psr.sink_psr2_support) return false; + if (crtc_state->cpu_transcoder != TRANSCODER_EDP) { + DRM_DEBUG_KMS("PSR2 is only supported in EDP transcoder\n"); + return false; + } + /* * DSC and PSR2 cannot be enabled simultaneously. If a requested * resolution requires DSC to be enabled, priority is given to DSC
According to PSR2_CTL definition on BSpec there is only one instance of PSR2_CTL also ICL display overview state that PSR2 is only supported in EDP transcoder, so now that is possible to have PSR in any transcoder lets add this hardware restriction. BSpec: 7713 BSpec: 20584 Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 5 +++++ 1 file changed, 5 insertions(+)