diff mbox series

[v6,1/3] drm/i915: fix whitelist selftests with readonly registers

Message ID 20190627090116.10847-2-lionel.g.landwerlin@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: CTS fixes | expand

Commit Message

Lionel Landwerlin June 27, 2019, 9:01 a.m. UTC
When a register is readonly there is not much we can tell about its
value (apart from its default value?). This can be covered by tests
exercising the value of the register from userspace.

For PS_INVOCATION_COUNT we've got the following piglit tests :

   KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations

Vulkan CTS tests :

   dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_workarounds.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Chris Wilson June 27, 2019, 11:57 a.m. UTC | #1
Quoting Lionel Landwerlin (2019-06-27 10:01:14)
> When a register is readonly there is not much we can tell about its
> value (apart from its default value?). This can be covered by tests
> exercising the value of the register from userspace.
> 
> For PS_INVOCATION_COUNT we've got the following piglit tests :
> 
>    KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations
> 
> Vulkan CTS tests :
> 
>    dEQP-VK.query_pool.statistics_query.fragment_shader_invocations.*
> 
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/selftest_workarounds.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> index f12cb20fe785..a06f96df1bfd 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> @@ -926,6 +926,9 @@ check_whitelisted_registers(struct intel_engine_cs *engine,
>  
>         err = 0;
>         for (i = 0; i < engine->whitelist.count; i++) {
> +               if (engine->whitelist.list[i].reg.reg & RING_FORCE_TO_NONPRIV_RD)

Ville would like you to use
i915_mmio_reg_offset(engine->whitelist.list[i].reg)

I think we might benefit from a reg local :)
-Chris
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index f12cb20fe785..a06f96df1bfd 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -926,6 +926,9 @@  check_whitelisted_registers(struct intel_engine_cs *engine,
 
 	err = 0;
 	for (i = 0; i < engine->whitelist.count; i++) {
+		if (engine->whitelist.list[i].reg.reg & RING_FORCE_TO_NONPRIV_RD)
+			continue;
+
 		if (!fn(engine, a[i], b[i], engine->whitelist.list[i].reg))
 			err = -EINVAL;
 	}