From patchwork Thu Jun 27 20:56:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 11020611 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 35CFA76 for ; Thu, 27 Jun 2019 20:58:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2BFC32870D for ; Thu, 27 Jun 2019 20:58:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2054928711; Thu, 27 Jun 2019 20:58:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BC6732870D for ; Thu, 27 Jun 2019 20:58:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8135A6E836; Thu, 27 Jun 2019 20:58:03 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id C69E96E867 for ; Thu, 27 Jun 2019 20:57:24 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Jun 2019 13:57:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,425,1557212400"; d="scan'208";a="164455819" Received: from unknown (HELO mwahaha-bdw.ger.corp.intel.com) ([10.252.4.227]) by fmsmga007.fm.intel.com with ESMTP; 27 Jun 2019 13:57:17 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Thu, 27 Jun 2019 21:56:31 +0100 Message-Id: <20190627205633.1143-36-matthew.auld@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190627205633.1143-1-matthew.auld@intel.com> References: <20190627205633.1143-1-matthew.auld@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 35/37] drm/i915/query: Expose memory regions through the query uAPI X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Abdiel Janulgue Returns the available memory region areas supported by the HW. Signed-off-by: Abdiel Janulgue Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_query.c | 57 +++++++++++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 39 +++++++++++++++++++++ 2 files changed, 96 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index 7b7016171057..21c4c2592d6c 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -143,10 +143,67 @@ query_engine_info(struct drm_i915_private *i915, return len; } +static int query_memregion_info(struct drm_i915_private *dev_priv, + struct drm_i915_query_item *query_item) +{ + struct drm_i915_query_memory_region_info __user *query_ptr = + u64_to_user_ptr(query_item->data_ptr); + struct drm_i915_memory_region_info __user *info_ptr = + &query_ptr->regions[0]; + struct drm_i915_memory_region_info info = { }; + struct drm_i915_query_memory_region_info query; + u32 total_length; + int ret, i; + + if (query_item->flags != 0) + return -EINVAL; + + total_length = sizeof(struct drm_i915_query_memory_region_info); + for (i = 0; i < ARRAY_SIZE(dev_priv->regions); ++i) { + struct intel_memory_region *region = dev_priv->regions[i]; + + if (!region) + continue; + + total_length += sizeof(struct drm_i915_memory_region_info); + } + + ret = copy_query_item(&query, sizeof(query), total_length, + query_item); + if (ret != 0) + return ret; + + if (query.num_regions || query.rsvd[0] || query.rsvd[1] || + query.rsvd[2]) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(dev_priv->regions); ++i) { + struct intel_memory_region *region = dev_priv->regions[i]; + + if (!region) + continue; + + info.id = region->id; + info.size = resource_size(®ion->region); + + if (__copy_to_user(info_ptr, &info, sizeof(info))) + return -EFAULT; + + query.num_regions++; + info_ptr++; + } + + if (__copy_to_user(query_ptr, &query, sizeof(query))) + return -EFAULT; + + return total_length; +} + static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, struct drm_i915_query_item *query_item) = { query_topology_info, query_engine_info, + query_memregion_info, }; int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file) diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 5cf976e7608a..9b77d8af9877 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -2041,6 +2041,7 @@ struct drm_i915_query_item { __u64 query_id; #define DRM_I915_QUERY_TOPOLOGY_INFO 1 #define DRM_I915_QUERY_ENGINE_INFO 2 +#define DRM_I915_QUERY_MEMREGION_INFO 3 /* Must be kept compact -- no holes and well documented */ /* @@ -2180,6 +2181,44 @@ struct drm_i915_query_engine_info { struct drm_i915_engine_info engines[]; }; +struct drm_i915_memory_region_info { + + /** Base type of a region + */ +#define I915_SYSTEM_MEMORY 0 +#define I915_DEVICE_MEMORY 1 + + /** The region id is encoded in a layout which makes it possible to + * retrieve the following information: + * + * Base type: log2(ID >> 16) + * Instance: log2(ID & 0xffff) + */ + __u32 id; + + /** Reserved field. MBZ */ + __u32 rsvd0; + + /** Unused for now. MBZ */ + __u64 flags; + + __u64 size; + + /** Reserved fields must be cleared to zero. */ + __u64 rsvd1[4]; +}; + +struct drm_i915_query_memory_region_info { + + /** Number of struct drm_i915_memory_region_info structs */ + __u32 num_regions; + + /** MBZ */ + __u32 rsvd[3]; + + struct drm_i915_memory_region_info regions[]; +}; + #if defined(__cplusplus) } #endif